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? 1999-2013 microchip technology inc. ds39026d-page 1 pic18cxx2 high performance risc cpu: ? c compiler optimized architecture/instruction set - source code compatible with the pic16cxx instruction set ? linear program memory addressing to 2 mbytes ? linear data memory addressing to 4 kbytes ? up to 10 mips operation: - dc - 40 mhz osc./clock input - 4 mhz - 10 mhz osc./clock input with pll active ? 16-bit wide instructions, 8-bit wide data path ? priority levels for interrupts ? 8 x 8 single cycle hardware multiplier peripheral features: ? high current sink/source 25 ma/25 ma ? three external interrupt pins ? timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler ? timer1 module: 16-bit timer/counter ? timer2 module: 8-bit timer/counter with 8-bit period register (time-base for pwm) ? timer3 module: 16-bit timer/counter ? secondary oscillator clock option - timer1/timer3 ? two capture/compare/pwm (ccp) modules. ccp pins that can be configured as: - capture input: capture is 16-bit, max. resolution 6.25 ns (t cy /16) - compare is 16-bit, max. resolution 100 ns (t cy ) - pwm output: pwm resolution is 1- to 10-bit. max. pwm freq. @: 8-bit resolution = 156 khz 10-bit resolution = 39 khz ? master synchronous serial port (mssp) module. two modes of operation: - 3-wire spi (supports all 4 spi modes) -i 2 c? master and slave mode ? addressable usart module: - supports interrupt on address bit ? parallel slave port (psp) module pin diagrams analog features: ? compatible 10-bit analog-to-digital converter module (a/d) with: - fast sampling rate - conversion available during sleep - dnl = 1 lsb, inl = 1 lsb ? programmable low voltage detection (lvd) module - supports interrupt-on-low voltage detection ? programmable brown-out reset (bor) special microcontroller features: ? power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? programmable code protection ? power saving sleep mode ? selectable oscillator options including: - 4x phase lock loop (of primary oscillator) - secondary oscillator (32 khz) clock input ? in-circuit serial programming (icsp?) via two pins cmos technology: ? low power, high speed eprom technology ? fully static design ? wide operating voltage range (2.5v to 5.5v) ? industrial and extended temperature ranges ? low power consumption device on-chip program memory on-chip ram (bytes) eprom (bytes) # single word instructions PIC18C242 16k 8192 512 pic18c252 32k 16384 1536 pic18c442 16k 8192 512 pic18c452 32k 16384 1536 rb7 rb6 rb5 rb4 rb3/ccp2 * rb2/int2 rb1/int1 rb0/int0 v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp ra0/an 0 ra1/an1 ra2/an2/v ref - ra3/an3/v ref + ra4/t0cki ra5/an4/ss /lvdin re0/rd/an5 re1/wr/an6 re2/cs/an7 v dd v ss osc1/clki osc2/clko/ra6 rc0/t1oso/t1cki rc1/t1osi/ccp2 * rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic18c4x2 * rb3 is the alternate pin for the ccp2 pin multiplexing. dip, windowed cerdip note: pin compatible with 40-pin pic16c7x devices. high performance microcon trollers with 10-bit a/d
pic18cxx2 ds39026d-page 2 ? 1999-2013 microchip technology inc. pin diagrams 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 8 7 6 5 4 3 2 1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 pic18c4x2 ra4/t0cki ra5/an4/ss /lvdin re0/rd /an5 osc2/clko/ra6 nc re1/wr/an6 re2/cs /an7 v dd osc1/clki rb3/ccp2 * rb2/int2 rb1/int1 rb0/int0 v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 mclr /v pp nc rb7 rb6 rb5 rb4 nc nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 * 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic18c4x2 37 ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 mclr /v pp nc rb7 rb6 rb5 rb4 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 * nc nc rc0/t1oso/t1cki osc2/clko/ra6 osc1/clki v ss v dd re2/an7/cs re1/an6/wr re0/an5/rd ra5/an4/ss /lvdin ra4/t0cki rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int0 rb1/int1 rb2/int2 rb3/ccp2 * plcc tqfp * rb3 is the alternate pin for the ccp2 pin multiplexing. note: pin compatible with 44-pin pic16c7x devices. v ss rc0/t1oso/t1cki
? 1999-2013 microchip technology inc. ds39026d-page 3 pic18cxx2 pin diagrams (cont.?d) rb7 rb6 rb5 rb4 rb3/ccp2 * rb2/int2 rb1/int1 rb0/int0 v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp ra0/an0 ra1/an1 ra2/an2/v ref - ra3/an3/v ref + ra4/t0cki ra5/an4/ss /lvdin re0/rd /an5 re1/wr /an6 re2/cs /an7 v dd v ss osc1/clki osc2/clko/ra6 rc0/t1oso/t1cki rc1/t1osi/ccp2 * rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic18c4x2 pic18c2x2 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr /v pp ra0/an0 ra1/an1 ra2/an2/v ref - ra3/an3/v ref + ra4/t0cki ra5/an4/ss /lvdin v ss osc1/clki osc2/clko/ra6 rc0/t1oso/t1cki rc1/t1osi/ccp2 * rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3/ccp2 * rb2/int2 rb1/int1 rb0/int0 v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda * rb3 is the alternate pin for the ccp2 pin multiplexing. dip, jw dip, soic, jw note: pin compatible with 40-pin pic16c7x devices. note: pin compatible with 28-pin pic16c7x devices.
pic18cxx2 ds39026d-page 4 ? 1999-2013 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................ 7 2.0 oscillator configurations................................................................................................... ........................................................ 17 3.0 reset....................................................................................................................... .................................................................. 25 4.0 memory organization......................................................................................................... ....................................................... 35 5.0 table reads/table writes .................................................................................................... .................................................... 55 6.0 8 x 8 hardware multiplier................................................................................................... ....................................................... 61 7.0 interrupts.................................................................................................................. ................................................................. 63 8.0 i/o ports................................................................................................................... ................................................................. 77 9.0 timer0 module ............................................................................................................... ........................................................... 93 10.0 timer1 module .............................................................................................................. ............................................................ 97 11.0 timer2 module .............................................................................................................. .......................................................... 101 12.0 timer3 module .............................................................................................................. .......................................................... 103 13.0 capture/compare/pwm (ccp) modules .......................................................................................... ...................................... 107 14.0 master synchronous serial port (mssp) module............................................................................... .................................... 115 15.0 addressable universal synchronous asynchr onous receiver transmitter (usart) ................................................ ............ 149 16.0 compatible 10-bit analog-to-digital converter (a/d) module ................................................................. ................................ 165 17.0 low voltage detect......................................................................................................... ........................................................ 173 18.0 special features of the cpu ................................................................................................ .................................................. 179 19.0 instruction set summary.................................................................................................... ..................................................... 187 20.0 development support ........................................................................................................ ..................................................... 229 21.0 electrical characteristics................................................................................................. ........................................................ 235 22.0 dc and ac characteristics graphs and tables ................................................................................ ..................................... 263 23.0 packaging information ...................................................................................................... ...................................................... 277 appendix a: revision history .................................................................................................... ..................................................... 287 appendix b: device differences.................................................................................................. ................................................... 287 appendix c: conversion considerations........................................................................................... ............................................. 288 appendix d: migration from baseline to enhanced devices ......................................................................... ................................. 288 appendix e: migration from mid-range to enhanced devices ........................................................................ .............................. 289 appendix f: migration from high-end to enhanced devices ......................................................................... ................................ 289 index .......................................................................................................................... ....................................................................... 291 on-line support................................................................................................................ ................................................................ 299 reader response ................................................................................................................ ............................................................. 300 pic18cxx2 product identification system ........................................................................................ ............................................... 301
? 1999-2013 microchip technology inc. ds39026d-page 5 pic18cxx2 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literatu re center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, pleas e specify which device, revisi on of silicon and data sheet (inclu de liter- ature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
pic18cxx2 ds39026d-page 6 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 7 pic18cxx2 1.0 device overview this document contains device specific information for the following four devices: 1. PIC18C242 2. pic18c252 3. pic18c442 4. pic18c452 these devices come in 28-pin and 40-pin packages. the 28-pin devices do not have a parallel slave port (psp) implemented and the number of analog-to- digital (a/d) converter input channels is reduced to 5. an overview of features is shown in table 1-1. the following two figures are device block diagrams sorted by pin count: 28-pin for figure 1-1 and 40-pin for figure 1-2. the 28-pin and 40-pin pinouts are listed in table 1-2 and table 1-3, respectively. table 1-1: device features features PIC18C242 pic18c252 pic18c442 pic18c452 operating frequency dc - 40 mhz dc - 40 mhz dc - 40 mhz dc - 40 mhz program memory (bytes) 16k 32k 16k 32k program memory (instructions) 8192 16384 8192 16384 data memory (bytes) 512 1536 512 1536 interrupt sources 16 16 17 17 i/o ports ports a, b, c ports a, b, c ports a, b, c, d, e ports a, b, c, d, e timers 44 44 capture/compare/pwm modules 2 2 2 2 serial communications mssp, addressable usart mssp, addressable usart mssp, addressable usart mssp, addressable usart parallel communications ? ? psp psp 10-bit analog-to-digital module 5 input channels 5 input channels 8 input channels 8 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) programmable low voltage detect yes yes yes yes programmable brown-out reset yes yes yes yes instruction set 75 instructions 75 instructions 75 instructions 75 instructions packages 28-pin dip 28-pin soic 28-pin jw 28-pin dip 28-pin soic 28-pin jw 40-pin dip 44-pin plcc 44-pin tqfp 40-pin jw 40-pin dip 44-pin plcc 44-pin tqfp 40-pin jw
pic18cxx2 ds39026d-page 8 ? 1999-2013 microchip technology inc. figure 1-1: pic18c2x2 block di agram power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control osc1/clki osc2/clko mclr v dd , v ss porta portb portc ra4/t0cki ra5/an4/ss /lvdin rb0/int0 rb7:rb4 rc0/t1oso/t1cki rc1/t1osi/ccp2 (1) rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt brown-out reset note 1: optional multiplexing of ccp2 input/output with rb3 is enabled by selection of configuration bit. 2: the high order bits of the direct address for the ram are from the bsr register (except for the movff instruction). 3: many of the general purpose i/o pins are multiplexed with one or more peripheral module functions. the multiplexing combination s are device dependent. addressable ccp1 synchronous timer0 timer1 timer2 serial port ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 timing generation 4x pll a/d converter precision reference rb1/int1 data latch data ram address latch address<12> 12 (2) bsr fsr0 fsr1 fsr2 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply wreg 8 bit op 8 8 alu<8> 8 address latch program memory (up to 2m bytes) data latch 20 21 21 16 8 8 8 inc/dec logic 21 8 data bus<8> 8 instruction 12 3 rom latch timer3 ccp2 rb2/int2 rb3/ccp2 (1) t1osi t1oso bank0, f pclatu pcu ra6 voltage usart master 8 register table latch table pointer <2> inc/dec logic decode
? 1999-2013 microchip technology inc. ds39026d-page 9 pic18cxx2 figure 1-2: pic18c4x2 block diagram power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control osc1/clki osc2/clko mclr v dd , v ss porta portb portc ra4/t0cki ra5/an4/ss /lvdin rb0/int0 rb7:rb4 rc0/t1oso/t1cki rc1/t1osi/ccp2 ( 1 ) rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt brown-out reset note 1: optional multiplexing of ccp2 input/output with rb3 is enabled by selection of configuration bit. 2: the high order bits of the direct address for the ram are from the bsr register (except for the movff instruction). 3: many of the general purpose i/o pins are multiplexed with one or more peripheral module functions. the multiplexing combination s are device dependent. addressable ccp1 master timer0 timer1 timer2 serial port ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 parallel slave port timing generation 4x pll a/d converter rb1/int1 data latch data ram (up to 4k address reach) address latch address<12> 12 (2) bank0, f bsr fsr0 fsr1 fsr2 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply wreg 8 bit op 8 8 alu<8> 8 address latch program memory (up to 2m bytes) data latch 20 21 21 16 8 8 8 inc/dec logic 21 8 data bus<8> 8 instruction 12 3 rom latch timer3 portd porte re0/an5/rd re1/an6/wr re2/an7/cs ccp2 rb2/int2 rb3/ccp2 (1) t1osi t1oso pclatu pcu ra6 precision reference voltage synchronous usart register 8 table pointer <2> inc/dec logic decode rd0/psp0 rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 table latch
pic18cxx2 ds39026d-page 10 ? 1999-2013 microchip technology inc. table 1-2: pic18c2x2 pinout i/o descriptions pin name pin number pin type buffer type description dip soic mclr /v pp mclr v pp 11 i p st master clear (input) or programming voltage (input). master clear (reset) input. this pin is an active low reset to the device. programming voltage input. nc ? ? ? ? these pins should be left unconnected. osc1/clki osc1 clki 99 i i st cmos oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode. cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clkin, osc2/clkout pins.) osc2/clko/ra6 osc2 clko ra6 10 10 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. general purpose i/o pin. porta is a bi-directional i/o port. ra0/an0 ra0 an0 22 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 33 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 44 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 55 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 66 i/o i st/od st digital i/o. open drain when configured as output. timer0 external clock input. ra5/an4/ss /lvdin ra5 an4 ss lvdin 77 i/o i i i ttl analog st analog digital i/o. analog input 4. spi slave select input. low voltage detect input. ra6 see the osc2/clko/ra6 pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open drain (no p diode to v dd )
? 1999-2013 microchip technology inc. ds39026d-page 11 pic18cxx2 portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0 rb0 int0 21 21 i/o i ttl st digital i/o. external interrupt 0. rb1/int1 rb1 int1 22 22 i/o i ttl st external interrupt 1. rb2/int2 rb2 int2 23 23 i/o i ttl st digital i/o. external interrupt 2. rb3/ccp2 rb3 ccp2 24 24 i/o i/o ttl st digital i/o. capture2 input, compare2 output, pwm2 output. rb4 25 25 i/o ttl digital i/o. interrupt-on-change pin. rb5 26 26 i/o ttl digital i/o. interrupt-on-change pin. rb6 27 27 i/o i ttl st digital i/o. interrupt-on-change pin. icsp programming clock. rb7 28 28 i/o i/o ttl st digital i/o. interrupt-on-change pin. icsp programming data. table 1-2: pic18c2x2 pinout i/o descriptions (continued) pin name pin number pin type buffer type description dip soic legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open drain (no p diode to v dd )
pic18cxx2 ds39026d-page 12 ? 1999-2013 microchip technology inc. portc is a bi-directional i/o port. rc0/t1oso/t1cki rc0 t1oso t1cki 11 11 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 12 12 i/o i i/o st cmos st digital i/o. timer1 oscillator input. capture2 input, compare2 output, pwm2 output. rc2/ccp1 rc2 ccp1 13 13 i/o i/o st st digital i/o. capture1 input/compare1 output/pwm1 output. rc3/sck/scl rc3 sck scl 14 14 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rc4/sdi/sda rc4 sdi sda 15 15 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 16 16 i/o o st ? digital i/o. spi data out. rc6/tx/ck rc6 tx ck 17 17 i/o o i/o st ? st digital i/o. usart asynchronous transmit. usart synchronous clock (see related rx/dt). rc7/rx/dt rc7 rx dt 18 18 i/o i i/o st st st digital i/o. usart asynchronous receive. usart synchronous data (see related tx/ck). v ss 8, 19 8, 19 p ? ground reference for logic and i/o pins. v dd 20 20 p ? positive supply for logic and i/o pins. table 1-2: pic18c2x2 pinout i/o descriptions (continued) pin name pin number pin type buffer type description dip soic legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open drain (no p diode to v dd )
? 1999-2013 microchip technology inc. ds39026d-page 13 pic18cxx2 table 1-3: pic18c4x2 pinout i/o descriptions pin name pin number pin type buffer type description dip plcc tqfp mclr /v pp mclr v pp 1218 i p st master clear (input) or programming voltage (input). master clear (reset) input. this pin is an active low reset to the device. programming voltage input. nc ? ? ? these pins should be left unconnected. osc1/clki osc1 clki 13 14 30 i i st cmos oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode, cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clkin, osc2/clkout pins.) osc2/clko/ra6 osc2 clko ra6 14 15 31 o o i/o ? ? ttl oscillator crystal output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. porta is a bi-directional i/o port. ra0/an0 ra0 an0 2319 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 3420 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 4521 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 5622 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 6723 i/o i st/od st digital i/o. open drain when configured as output. timer0 external clock input. ra5/an4/ss /lvdin ra5 an4 ss lvdin 7824 i/o i i i ttl analog st analog digital i/o. analog input 4. spi slave select input. low voltage detect input. ra6 see the osc2/clko/ra6 pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open drain (no p diode to v dd )
pic18cxx2 ds39026d-page 14 ? 1999-2013 microchip technology inc. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0 rb0 int0 33 36 8 i/o i ttl st digital i/o. external interrupt 0. rb1/int1 rb1 int1 34 37 9 i/o i ttl st external interrupt 1. rb2/int2 rb2 int2 35 38 10 i/o i ttl st digital i/o. external interrupt 2. rb3/ccp2 rb3 ccp2 36 39 11 i/o i/o ttl st digital i/o. capture2 input, compare2 output, pwm2 output. rb4 37 41 14 i/o ttl digital i/o. interrupt-on-change pin. rb5 38 42 15 i/o ttl digital i/o. interrupt-on-change pin. rb6 39 43 16 i/o i ttl st digital i/o. interrupt-on-change pin. icsp programming clock. rb7 40 44 17 i/o i/o ttl st digital i/o. interrupt-on-change pin. icsp programming data. table 1-3: pic18c4x2 pinout i/o descriptions (continued) pin name pin number pin type buffer type description dip plcc tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open drain (no p diode to v dd )
? 1999-2013 microchip technology inc. ds39026d-page 15 pic18cxx2 portc is a bi-directional i/o port. rc0/t1oso/t1cki rc0 t1oso t1cki 15 16 32 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 16 18 35 i/o i i/o st cmos st digital i/o. timer1 oscillator input. capture2 input, compare2 output, pwm2 output. rc2/ccp1 rc2 ccp1 17 19 36 i/o i/o st st digital i/o. capture1 input/compare1 output/pwm1 output. rc3/sck/scl rc3 sck scl 18 20 37 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rc4/sdi/sda rc4 sdi sda 23 25 42 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 24 26 43 i/o o st ? digital i/o. spi data out. rc6/tx/ck rc6 tx ck 25 27 44 i/o o i/o st ? st digital i/o. usart asynchronous transmit. usart synchronous clock (see related rx/dt). rc7/rx/dt rc7 rx dt 26 29 1 i/o i i/o st st st digital i/o. usart asynchronous receive. usart synchronous data (see related tx/ck). table 1-3: pic18c4x2 pinout i/o descriptions (continued) pin name pin number pin type buffer type description dip plcc tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open drain (no p diode to v dd )
pic18cxx2 ds39026d-page 16 ? 1999-2013 microchip technology inc. portd is a bi-directional i/o port, or a parallel slave port (psp) for interfacing to a microprocessor port. these pins have ttl input buffers when psp module is enabled. rd0/psp0 19 21 38 i/o st ttl digital i/o. parallel slave port data. rd1/psp1 20 22 39 i/o st ttl digital i/o. parallel slave port data. rd2/psp2 21 23 40 i/o st ttl digital i/o. parallel slave port data. rd3/psp3 22 24 41 i/o st ttl digital i/o. parallel slave port data. rd4/psp4 27 30 2 i/o st ttl digital i/o. parallel slave port data. rd5/psp5 28 31 3 i/o st ttl digital i/o. parallel slave port data. rd6/psp6 29 32 4 i/o st ttl digital i/o. parallel slave port data. rd7/psp7 30 33 5 i/o st ttl digital i/o. parallel slave port data. porte is a bi-directional i/o port. re0/rd /an5 re0 rd an5 8925i/o st ttl analog digital i/o. read control for parallel slave port (see also wr and cs pins). analog input 5. re1/wr /an6 re1 wr an6 91026i/o st ttl analog digital i/o. write control for parallel slave port (see cs and rd pins). analog input 6. re2/cs /an7 re2 cs an7 10 11 27 i/o st ttl analog digital i/o. chip select control for parallel slave port (see related rd and wr ). analog input 7. v ss 12, 31 13, 34 6, 29 p ? ground reference for logic and i/o pins. v dd 11, 32 12, 35 7, 28 p ? positive supply for logic and i/o pins. table 1-3: pic18c4x2 pinout i/o descriptions (continued) pin name pin number pin type buffer type description dip plcc tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open drain (no p diode to v dd )
? 1999-2013 microchip technology inc. ds39026d-page 17 pic18cxx2 2.0 oscillator configurations 2.1 oscillator types the pic18cxx2 can be operated in eight different oscillator modes. the user can program three configu- ration bits (fosc2, fosc1, and fosc0) to select one of these eight modes: 1. lp low power crystal 2. xt crystal/resonator 3. hs high speed crystal/resonator 4. hs + pll high speed crystal/resonator with x 4 pll enabled 5. rc external resistor/capacitor 6. rcio external resistor/capacitor with ra6 i/o pin enabled 7. ec external clock 8. ecio external clock with ra6 i/o pin enabled 2.2 crystal oscillator/ceramic resonators in xt, lp, hs or hs-pll oscillator modes, a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation. figure 2-1 shows the pin connections. the pic18cxx2 oscillator design requires the use of a parallel cut crystal. figure 2-1: crystal/ceramic resonator operation (hs, xt or lp osc configuration) table 2-1: capacitor selection for ceramic resonators note: use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. note 1: see table 2-1 and table 2-2 for recom- mended values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the osc mode chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic pic18cxxx r s (2) internal ranges tested: mode freq c1 c2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these values are for design guidance only. see notes following this table. resonators used: 455 khz panasonic efo-a455k04b ? 0.3% 2.0 mhz murata erie csa2.00mg ? 0.5% 4.0 mhz murata erie csa4.00mg ? 0.5% 8.0 mhz murata erie csa8.00mt ? 0.5% 16.0 mhz murata erie csa16.00mx ? 0.5% all resonators used did not have built-in capacitors. note 1: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: when operating below 3v v dd , it may be necessary to use high gain hs mode on lower frequency ceramic resonators. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external compo- nents or verify oscillator performance.
pic18cxx2 ds39026d-page 18 ? 1999-2013 microchip technology inc. table 2-2: capacitor selection for crystal oscillators an external clock source may also be connected to the osc1 pin in these modes, as shown in figure 2-2. figure 2-2: external clock input operation (hs, xt or lp configuration) 2.3 rc oscillator for timing insensitive applications, the ?rc? and "rcio" device options offer additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) val- ues and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, espe- cially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 2-3 shows how the r/c combination is connected. in the rc oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-3: rc oscillator mode the rcio oscillator mode functions like the rc mode, except that the osc2 pin becomes an additional gen- eral purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). ranges tested: mode freq c1 c2 lp 32.0 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1.0 mhz 15 pf 15 pf 4.0 mhz 15 pf 15 pf hs 4.0 mhz 15 pf 15 pf 8.0 mhz 15-33 pf 15-33 pf 20.0 mhz 15-33 pf 15-33 pf 25.0 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes following this table. crystals used 32.0 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1.0 mhz ecs ecs-10-13-1 50 ppm 4.0 mhz ecs ecs-40-20-1 50 ppm 8.0 mhz epson ca-301 8.000m-c 30 ppm 20.0 mhz epson ca-301 20.000m-c 30 ppm note 1: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external compo- nents or verify oscillator performance. osc1 osc2 open clock from ext. system pic18cxxx osc2/clko c ext r ext pic18cxxx osc1 f osc /4 internal clock v dd v ss recommended values:3 k ? ? r ext ? 100 k ? c ext > 20pf
? 1999-2013 microchip technology inc. ds39026d-page 19 pic18cxx2 2.4 external clock input the ec and ecio oscillator modes require an external clock source to be connected to the osc1 pin. the feedback device between osc1 and osc2 is turned off in these modes to save current. there is no oscilla- tor start-up time required after a power-on reset or after a recovery from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-4 shows the pin connections for the ec oscillator mode. figure 2-4: exter nal clock input operation (ec osc configuration) the ecio oscillator mode functions like the ec mode, except that the osc2 pin becomes an additional gen- eral purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 2-5 shows the pin connections for the ecio oscillator mode. figure 2-5: external clock input operation (ecio configuration) 2.5 hs/pll a phase locked loop circuit is provided as a program- mable option for users that want to multiply the fre- quency of the incoming crystal oscillator signal by 4. for an input clock frequency of 10 mhz, the internal clock frequency will be multiplied to 40 mhz. this is useful for customers who are concerned with emi due to high frequency crystals. the pll can only be enabled when the oscillator con- figuration bits are programmed for hs mode. if they are programmed for any other mode, the pll is not enabled and the system clock will come directly from osc1. the pll is one of the modes of the fosc<2:0> config- uration bits. the oscillator mode is specified during device programming. a pll lock timer is used to ensure that the pll has locked before device execution starts. the pll lock timer has a time-out that is called t pll . figure 2-6: pll block diagram osc1 osc2 f osc /4 clock from ext. system pic18cxxx osc1 i/o (osc2) ra6 clock from ext. system pic18cxxx mux vco loop filter divide by 4 crystal osc osc1 pll enable f in f out sysclk phase comparator (from configuration hs osc bit register) osc2
pic18cxx2 ds39026d-page 20 ? 1999-2013 microchip technology inc. 2.6 oscillator switching feature the pic18cxx2 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. for the pic18cxx2 devices, this alternate clock source is the timer1 oscillator. if a low frequency crys- tal (32 khz, for example) has been attached to the timer1 oscillator pins and the timer1 oscillator has been enabled, the device can switch to a low power execution mode. figure 2-7 shows a block diagram of the system clock sources. the clock switching feature is enabled by programming the oscillator switching enable (oscsen ) bit in configuration register1h to a ?0?. clock switching is disabled in an erased device. see section 9.0 for further details of the timer1 oscilla- tor. see section 18.0 for configuration register details. figure 2-7: device clock sources 2.6.1 system clock switch bit the system clock source switching is performed under software control. the system clock switch bit, scs (osccon<0>) controls the clock switching. when the scs bit is?0?, the system clock source comes from the main oscillator that is selected by the fosc configura- tion bits in configuration register1h. when the scs bit is set, the system clock source will come from the timer1 oscillator. the scs bit is cleared on all forms of reset. register 2-1: osccon register pic18cxxx t osc 4 x pll t t 1 p t sclk clock source mux t osc /4 timer1 oscillator t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep main oscillator note: the timer1 oscillator must be enabled and operating to switch the system clock source. the timer1 oscillator is enabled by setting the t1oscen bit in the timer1 control register (t1con). if the timer1 oscillator is not enabled, then any write to the scs bit will be ignored (scs bit forced cleared) and the main oscillator will con- tinue to be the system clock source. u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-1 ? ? ? ? ? ? ?scs bit 7 bit 0 bit 7-1 unimplemented: read as '0' bit 0 scs: system clock switch bit when oscsen configuration bit = ?0? and t1oscen bit is set: 1 = switch to timer1 oscillator/clock pin 0 = use primary oscillator/clock input pin when oscsen and t1oscen are in other states: bit is forced clear legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1999-2013 microchip technology inc. ds39026d-page 21 pic18cxx2 2.6.2 oscillator transitions the pic18cxx2 devices contain circuitry to prevent "glitches" when switching between oscillator sources. essentially, the circuitry waits for eight rising edges of the clock source that the processor is switching to. this ensures that the new clock source is stable and that it?s pulse width will not be less than the shortest pulse width of the two clock sources. a timing diagram indicating the transition from the main oscillator to the timer1 oscillator is shown in figure 2-8. the timer1 oscillator is assumed to be run- ning all the time. after the scs bit is set, the processor is frozen at the next occurring q1 cycle. after eight syn- chronization cycles are counted from the timer1 oscil- lator, operation resumes. no additional delays are required after the synchronization cycles. figure 2-8: timing diagram for transition from osc1 to timer1 oscillator the sequence of events that takes place when switch- ing from the timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. in addition to eight clock cycles of the main oscillator, additional delays may take place. if the main oscillator is configured for an external crys- tal (hs, xt, lp), then the transition will take place after an oscillator start-up time (t ost ) has occurred. a timing diagram indicating the transition from the timer1 oscil- lator to the main oscillator for hs, xt and lp modes is shown in figure 2-9. figure 2-9: timing for transition be tween timer1 and osc1 (hs, xt, lp) q3 q2 q1 q4 q3 q2 osc1 internal scs (osccon<0>) program pc + 2 pc note 1: delay on internal system clock is eight oscillator cycles for synchronization. q1 t1osi q4 q1 pc + 4 q1 ts cs clock counter system q2 q3 q4 q1 t dly t t 1 p t osc 2 1 34 5678 q3 q3 q4 q1 q2 q3 q4 q1 q2 osc1 internal system scs (osccon<0>) program counter pc pc + 2 note 1: t ost = 1024t osc (drawing not to scale). t1osi clock osc2 t ost q1 pc + 6 t t 1 p t osc t scs 1234 5678
pic18cxx2 ds39026d-page 22 ? 1999-2013 microchip technology inc. if the main oscillator is configured for hs-pll mode, an oscillator start-up time (t ost ) plus an additional pll time-out (t pll ) will occur. the pll time-out is typically 2 ms and allows the pll to lock to the main oscillator frequency. a timing diagram, indicating the transition from the timer1 oscillator to the main oscillator for hs-pll mode, is shown in figure 2-10. figure 2-10: timing for transition between timer1 and osc1 (hs with pll) if the main oscillator is configured in the rc, rcio, ec or ecio modes, there is no oscillator start-up time-out. operation will resume after eight cycles of the main oscillator have been counted. a timing diagram, indi- cating the transition from the timer1 oscillator to the main oscillator for rc, rcio, ec and ecio modes, is shown in figure 2-11. figure 2-11: timing for transition between timer1 and osc1 (rc, ec) q4 q1 q1 q2 q3 q4 q1 q2 osc1 internal system scs (osccon<0>) program counter pc pc + 2 note 1: t ost = 1024t osc (drawing not to scale). t1osi clock t ost q3 pc + 4 t pll t osc t t 1 p t scs q4 osc2 pll clock input 1 234 5678 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 osc1 internal system scs (osccon<0>) program counter pc pc + 2 note 1: rc oscillator mode assumed. pc + 4 t1osi clock osc2 q4 t t 1 p t osc t scs 1 23 45 6 78
? 1999-2013 microchip technology inc. ds39026d-page 23 pic18cxx2 2.7 effects of sleep mode on the on-chip oscillator when the device executes a sleep instruction, the on-chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (q1 state). with the oscillator off, the osc1 and osc2 signals will stop oscillating. since all the transistor switching currents have been removed, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the user can wake from sleep through external reset, watchdog timer reset, or through an interrupt. table 2-3: osc1 and osc2 pin states in sleep mode 2.8 power-up delays power up delays are controlled by two timers, so that no external reset circuitry is required for most appli- cations. the delays ensure that the device is kept in reset until the device power supply and clock are sta- ble. for additional information on reset operation, see the ?reset? section. the first timer is the power-up timer (pwrt), which optionally provides a fixed delay of 72 ms (nominal) on power-up only (por and bor). the second timer is the oscillator start-up timer, ost, intended to keep the chip in reset until the crystal oscillator is stable. with the pll enabled (hs/pll oscillator mode), the time-out sequence following a power-on reset is differ- ent from other oscillator modes. the time-out sequence is as follows: first, the pwrt time-out is invoked after a por time delay has expired. then, the oscillator start-up timer (ost) is invoked. however, this is still not a sufficient amount of time to allow the pll to lock at high frequencies. the pwrt timer is used to provide an additional fixed 2ms (nominal) time-out to allow the pll ample time to lock to the incoming clock frequency. osc mode osc1 pin osc2 pin rc floating, external resistor should pull high at logic low rcio floating, external resistor should pull high configured as porta, bit 6 ecio floating configured as porta, bit 6 ec floating at logic low lp, xt, and hs feedback inverter disabled, at quiescent voltage level feedback inverter disabled, at quiescent voltage level note: see table 3-1, in section 3.0 reset, for time-outs due to sleep and mclr reset.
pic18cxx2 ds39026d-page 24 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 25 pic18cxx2 3.0 reset the pic18cxx2 differentiates between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) watchdog timer (wdt) reset (during normal operation) e) programmable brown-out reset (bor) f) reset instruction g) stack full reset h) stack underflow reset most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a ?reset state? on power-on reset, mclr , wdt reset, brown- out reset, mclr reset during sleep, and by the reset instruction. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal oper- ation. status bits from the rcon register, ri , to , pd , por and bor, are set or cleared differently in different reset situations, as indicated in table 3-2. these bits are used in software to determine the nature of the reset. see table 3-3 for a full description of the reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 3-1. the enhanced mcu devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. mclr pin is not driven low by any internal resets, including wdt. figure 3-1: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc (1) wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost (2) enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clkin pin. 2: see table 3-1 for time-out situations. brown-out reset boren reset instruction stack pointer stack full/underflow reset
pic18cxx2 ds39026d-page 26 ? 1999-2013 microchip technology inc. 3.1 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected. to take advantage of the por cir- cuitry, just tie the mclr pin directly (or through a resis- tor) to v dd . this will eliminate external rc components usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified (parameter d004). for a slow rise time, see figure 3-2. when the device starts normal operation (i.e., exits the reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating condi- tions are met. figure 3-2: exte rnal power-on reset circuit (for slow v dd power-up) 3.2 power-up timer (pwrt) the power-up timer provides a fixed nominal time-out (parameter #33) only on power-up from the por. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrt?s time delay allows v dd to rise to an accept- able level. a configuration bit is provided to enable/ disable the pwrt. the power-up time delay will vary from chip-to-chip due to v dd , temperature and process variation. see dc parameter #33 for details. 3.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over (parameter #32). this ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 3.4 pll lock time-out with the pll enabled, the time-out sequence following a power-on reset is different from other oscillator modes. a portion of the power-up timer is used to pro- vide a fixed time-out that is sufficient for the pll to lock to the main oscillator frequency. this pll lock time-out (t pll ) is typically 2 ms and follows the oscillator start- up time-out (ost). 3.5 brown-out reset (bor) a configuration bit, boren, can disable (if clear/ programmed), or enable (if set) the brown-out reset circuitry. if v dd falls below parameter d005 for greater than parameter #35, the brown-out situation will reset the chip. a reset may not occur if v dd falls below parameter d005 for less than parameter #35. the chip will remain in brown-out reset until v dd rises above bv dd . the power-up timer will then be invoked and will keep the chip in reset an additional time delay (parameter #33). if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initial- ized. once v dd rises above bv dd , the power-up timer will execute the additional time delay. 3.6 time-out sequence on power-up, the time-out sequence is as follows: first, pwrt time-out is invoked after the por time delay has expired. then, ost is activated. the total time-out will vary based on oscillator configuration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. figure 3-3, figure 3-4, figure 3-5, figure 3-6 and figure 3-7 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. bringing mclr high will begin execution immediately (figure 3-5). this is useful for testing purposes or to synchronize more than one pic18cxxx device oper- ating in parallel. table 3-2 shows the reset conditions for some special function registers, while table 3-3 shows the reset conditions for all the registers. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that the voltage drop across r does not violate the device?s electrical specification. 3: r1 = 100 ? to 1 k ? will limit any current flow- ing into mclr from external capacitor c in the event of mclr/ v pp pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic18cxxx
? 1999-2013 microchip technology inc. ds39026d-page 27 pic18cxx2 table 3-1: time-out in va rious situations register 3-1: rcon register bits and positions table 3-2: status bits, their significanc e and the initialization condition for rcon register oscillator configuration power-up (2) brown-out (2) wake-up from sleep or oscillator switch pwrte = 0 pwrte = 1 hs with pll enabled (1) 72 ms + 1024t osc + 2ms 1024t osc + 2 ms 72 ms + 1024t osc + 2ms 1024t osc + 2 ms hs, xt, lp 72 ms + 1024t osc 1024t osc 72 ms + 1024t osc 1024t osc ec 72 ms ? 72 ms ? external rc 72 ms ? 72 ms ? note 1: 2 ms is the nominal time required for the 4x pll to lock. 2: 72 ms is the nominal power-up timer delay. r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 ipen lwrt ?ri to pd por bor bit 7 bit 0 note: see register 4-3 on page 53 for bit definitions. condition program counter rcon register ri to pd por bor stkful stkunf power-on reset 0000h 00-1 1100 1 1 1 0 0 u u mclr reset during normal operation 0000h 00-u uuuu u u u u u u u software reset during normal operation 0000h 0u-0 uuuu 0 u u u u u u stack full reset during normal operation 0000h 0u-u uu11 u u u u u u 1 stack underflow reset during normal operation 0000h 0u-u uu11 u u u u u 1 u mclr reset during sleep 0000h 00-u 10uu u 1 0 u u u u wdt reset 0000h 0u-u 01uu 1 0 1 u u u u wdt wake-up pc + 2 uu-u 00uu u 0 0 u u u u brown-out reset 0000h 0u-1 11u0 1 1 1 1 0 u u interrupt wake-up from sleep pc + 2 (1) uu-u 00uu u 1 0 u u u u legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'. note 1: when the wake-up is due to an interrupt and the gieh or giel bits are set, the pc is loaded with the interrupt vector ( 0x000008h or 0x000018h ).
pic18cxx2 ds39026d-page 28 ? 1999-2013 microchip technology inc. table 3-3: initialization co nditions for all registers register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt tosu 242 442 252 452 ---0 0000 ---0 0000 ---0 uuuu (3) tosh 242 442 252 452 0000 0000 0000 0000 uuuu uuuu (3) tosl 242 442 252 452 0000 0000 0000 0000 uuuu uuuu (3) stkptr 242 442 252 452 00-0 0000 00-0 0000 uu-u uuuu (3) pclatu 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu pclath 242 442 252 452 0000 0000 0000 0000 uuuu uuuu pcl 242 442 252 452 0000 0000 0000 0000 pc + 2 (2) tblptru 242 442 252 452 --00 0000 --00 0000 --uu uuuu tblptrh 242 442 252 452 0000 0000 0000 0000 uuuu uuuu tblptrl 242 442 252 452 0000 0000 0000 0000 uuuu uuuu tablat 242 442 252 452 0000 0000 0000 0000 uuuu uuuu prodh 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu prodl 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu intcon 242 442 252 452 0000 000x 0000 000u uuuu uuuu (1) intcon2 242 442 252 452 1111 -1-1 1111 -1-1 uuuu -u-u (1) intcon3 242 442 252 452 11-0 0-00 11-0 0-00 uu-u u-uu (1) indf0 242 442 252 452 n/a n/a n/a postinc0 242 442 252 452 n/a n/a n/a postdec0 242 442 252 452 n/a n/a n/a preinc0 242 442 252 452 n/a n/a n/a plusw0 242 442 252 452 n/a n/a n/a fsr0h 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu fsr0l 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu wreg 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu indf1 242 442 252 452 n/a n/a n/a postinc1 242 442 252 452 n/a n/a n/a postdec1 242 442 252 452 n/a n/a n/a preinc1 242 442 252 452 n/a n/a n/a plusw1 242 442 252 452 n/a n/a n/a legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hard- ware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata, and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ?0?. 6: the long write enable is only reset on a por or mclr reset. 7: bit 6 of porta, lata and trisa are not available on a ll devices. when unimplemented, they are read as ?0?.
? 1999-2013 microchip technology inc. ds39026d-page 29 pic18cxx2 fsr1h 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu fsr1l 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu bsr 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu indf2 242 442 252 452 n/a n/a n/a postinc2 242 442 252 452 n/a n/a n/a postdec2 242 442 252 452 n/a n/a n/a preinc2 242 442 252 452 n/a n/a n/a plusw2 242 442 252 452 n/a n/a n/a fsr2h 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu fsr2l 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu status 242 442 252 452 ---x xxxx ---u uuuu ---u uuuu tmr0h 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu tmr0l 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu t0con 242 442 252 452 1111 1111 1111 1111 uuuu uuuu osccon 242 442 252 452 ---- ---0 ---- ---0 ---- ---u lvdcon 242 442 252 452 --00 0101 --00 0101 --uu uuuu wdtcon 242 442 252 452 ---- ---0 ---- ---0 ---- ---u rcon (4, 6) 242 442 252 452 00-1 11q0 00-1 qquu uu-u qquu tmr1h 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu tmr1l 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu t1con 242 442 252 452 0-00 0000 u-uu uuuu u-uu uuuu tmr2 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu pr2 242 442 252 452 1111 1111 1111 1111 1111 1111 t2con 242 442 252 452 -000 0000 -000 0000 -uuu uuuu sspbuf 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu sspadd 242 442 252 452 0000 0000 0000 0000 uuuu uuuu sspstat 242 442 252 452 0000 0000 0000 0000 uuuu uuuu sspcon1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu sspcon2 242 442 252 452 0000 0000 0000 0000 uuuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hard- ware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata, and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ?0?. 6: the long write enable is only reset on a por or mclr reset. 7: bit 6 of porta, lata and trisa are not available on a ll devices. when unimplemented, they are read as ?0?.
pic18cxx2 ds39026d-page 30 ? 1999-2013 microchip technology inc. adresh 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu adresl 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 242 442 252 452 0000 0000 0000 0000 uuuu uuuu adcon1 242 442 252 452 --0- 0000 --0- 0000 --u- uuuu ccpr1h 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1l 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 242 442 252 452 --00 0000 --00 0000 --uu uuuu ccpr2h 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu ccpr2l 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 242 442 252 452 --00 0000 --00 0000 --uu uuuu tmr3h 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu tmr3l 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu t3con 242 442 252 452 0000 0000 uuuu uuuu uuuu uuuu spbrg 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu rcreg 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu txreg 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu txsta 242 442 252 452 0000 -01x 0000 -01u uuuu -uuu rcsta 242 442 252 452 0000 000x 0000 000u uuuu uuuu ipr2 242 442 252 452 ---- 1111 ---- 1111 ---- uuuu pir2 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu (1) pie2 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu ipr1 242 442 252 452 1111 1111 1111 1111 uuuu uuuu 242 442 252 452 -111 1111 -111 1111 -uuu uuuu pir1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu (1) 242 442 252 452 -000 0000 -000 0000 -uuu uuuu (1) pie1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu 242 442 252 452 -000 0000 -000 0000 -uuu uuuu table 3-3: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hard- ware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata, and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ?0?. 6: the long write enable is only reset on a por or mclr reset. 7: bit 6 of porta, lata and trisa are not available on a ll devices. when unimplemented, they are read as ?0?.
? 1999-2013 microchip technology inc. ds39026d-page 31 pic18cxx2 trise 242 442 252 452 0000 -111 0000 -111 uuuu -uuu trisd 242 442 252 452 1111 1111 1111 1111 uuuu uuuu trisc 242 442 252 452 1111 1111 1111 1111 uuuu uuuu trisb 242 442 252 452 1111 1111 1111 1111 uuuu uuuu trisa (5, 7) 242 442 252 452 -111 1111 (5) -111 1111 (5) -uuu uuuu (5) late 242 442 252 452 ---- -xxx ---- -uuu ---- -uuu latd 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu latc 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu latb 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu lata (5, 7) 242 442 252 452 -xxx xxxx (5) -uuu uuuu (5) -uuu uuuu (5) porte 242 442 252 452 ---- -000 ---- -000 ---- -uuu portd 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu portc 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu portb 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu porta (5, 7) 242 442 252 452 -x0x 0000 (5) -u0u 0000 (5) -uuu uuuu (5) table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hard- ware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata, and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ?0?. 6: the long write enable is only reset on a por or mclr reset. 7: bit 6 of porta, lata and trisa are not available on a ll devices. when unimplemented, they are read as ?0?.
pic18cxx2 ds39026d-page 32 ? 1999-2013 microchip technology inc. figure 3-3: time-out sequ ence on power-up (mclr tied to v dd ) figure 3-4: time-out sequ ence on power-up (mclr not tied to v dd ): case 1 figure 3-5: time-out sequ ence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
? 1999-2013 microchip technology inc. ds39026d-page 33 pic18cxx2 figure 3-6: slow rise time (mclr tied to v dd ) figure 3-7: time-out sequence on por w/ pll enabled (mclr tied to v dd ) v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost t pwrt t ost v dd mclr iinternal por pwrt time-out ost time-out internal reset pll time-out t pll note: t ost = 1024 clock cycles. t pll ? 2 ms max. first three stages of the pwrt timer.
pic18cxx2 ds39026d-page 34 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 35 pic18cxx2 4.0 memory organization there are two memory blocks in enhanced mcu devices. these memory blocks are: ? program memory ? data memory program and data memory use separate buses so that concurrent access can occur. 4.1 program memory organization a 21-bit program counter is capable of addressing the 2-mbyte program memory space. accessing a location between the physically implemented memory and the 2-mbyte address will cause a read of all ?0?s (a nop instruction). pic18c252 and pic18c452 have 32 kbytes of eprom, while PIC18C242 and pic18c442 have 16 kbytes of eprom. this means that pic18cx52 devices can store up to 16k of single word instructions, and pic18cx42 devices can store up to 8k of single word instructions. the reset vector address is at 0000h and the inter- rupt vector addresses are at 0008h and 0018h. figure 4-1 shows the program memory map for PIC18C242/442 devices and figure 4-2 shows the program memory map for pic18c252/452 devices.
pic18cxx2 ds39026d-page 36 ? 1999-2013 microchip technology inc. figure 4-1: program memory map and stack for pic18c442/242 figure 4-2: program memory map and stack for pic18c452/252 pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? call,rcall,return retfie,retlw 21 0000h 0018h on-chip program memory high priority interrupt vector 0008h user memory space 1fffffh 4000h 3fffh read '0' 200000h pc<20:0> stack level 1 ? stack level 31 low priority interrupt vector ? ? call,rcall,return retfie,retlw 21 0000h 0018h 8000h 7fffh on-chip program memory high priority interrupt vector 0008h user memory space read '0' 1fffffh 200000h reset vector
? 1999-2013 microchip technology inc. ds39026d-page 37 pic18cxx2 4.2 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc (program counter) is pushed onto the stack when a call or rcall instruction is executed, or an interrupt is acknowledged. the pc value is pulled off the stack on a return, retlw or a retfie instruction. pclatu and pclath are not affected by any of the call or return instructions. the stack operates as a 31-word by 21-bit ram and a 5-bit stack pointer, with the stack pointer initialized to 00000b after all resets. there is no ram associated with stack pointer 00000b. this is only a reset value. during a call type instruction causing a push onto the stack, the stack pointer is first incremented and the ram location pointed to by the stack pointer is written with the contents of the pc. during a return type instruction causing a pop from the stack, the contents of the ram location pointed to by the stkptr is trans- ferred to the pc and then the stack pointer is decremented. the stack space is not part of either program or data space. the stack pointer is readable and writable, and the address on the top of the stack is readable and writ- able through sfr registers. data can also be pushed to, or popped from, the stack, using the top-of-stack sfrs. status bits indicate if the stack pointer is at, or beyond the 31 levels provided. 4.2.1 top-of-stack access the top of the stack is readable and writable. three register locations, tosu, tosh and tosl hold the contents of the stack location pointed to by the stkptr register. this allows users to implement a software stack, if necessary. after a call, rcall or interrupt, the software can read the pushed value by reading the tosu, tosh and tosl registers. these values can be placed on a user defined software stack. at return time, the software can replace the tosu, tosh and tosl and do a return. the user must disable the global interrupt enable bits during this time to prevent inadvertent stack opera- tions. . 4.2.2 return stack pointer (stkptr) the stkptr register contains the stack pointer value, the stkful (stack full) status bit, and the stkunf (stack underflow) status bits. register 4-1 shows the stkptr register. the value of the stack pointer can be 0 through 31. the stack pointer increments when val- ues are pushed onto the stack and decrements when values are popped off the stack. at reset, the stack pointer value will be 0. the user may read and write the stack pointer value. this feature can be used by a real time operating system for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit can only be cleared in software or by a por. the action that takes place when the stack becomes full, depends on the state of the stvren (stack over- flow reset enable) configuration bit. refer to section 18.0 for a description of the device configura- tion bits. if stvren is set (default), the 31st push will push the (pc + 2) value onto the stack, set the stkful bit, and reset the device. the stkful bit will remain set and the stack pointer will be set to 0. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. any additional pushes will not overwrite the 31st push and stkptr will remain at 31. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and sets the stkunf bit, while the stack pointer remains at 0. the stkunf bit will remain set until cleared in software or a por occurs. note: returning a value of zero to the pc on an underflow, has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appro- priate actions can be taken.
pic18cxx2 ds39026d-page 38 ? 1999-2013 microchip technology inc. register 4-1: stkptr register figure 4-3: return address stack and associated registers 4.2.3 push and pop instructions since the top-of-stack (tos) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execu- tion, is a desirable option. to push the current pc value onto the stack, a push instruction can be executed. this will increment the stack pointer and load the cur- rent pc value onto the stack. tosu, tosh and tosl can then be modified to place a return address on the stack. the ability to pull the tos value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the pop instruction. the pop instruc- tion discards the current tos by decrementing the stack pointer. the previous value pushed onto the stack then becomes the tos value. 4.2.4 stack full/underflow resets these resets are enabled by programming the stvren configuration bit. when the stvren bit is disabled, a full or underflow condition will set the appro- priate stkful or stkunf bit, but not cause a device reset. when the stvren bit is enabled, a full or underflow will set the appropriate stkful or stkunf bit and then cause a device reset. the stkful or stkunf bits are only cleared by the user software or a por reset. r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful stkunf ? sp4 sp3 sp2 sp1 sp0 bit 7 bit 0 bit 7 (1) stkful : stack full flag bit 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 (1) stkunf : stack underflow flag bit 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented : read as '0' bit 4-0 sp4:sp0 : stack pointer location bits note 1: bit 7 and bit 6 can only be cleared in user software or by a por. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown 00011 0x001a34 11111 11110 11101 00010 00001 00000 00010 return address stack top-of-stack 0x000d58 tosl tosh tosu 0x34 0x1a 0x00 stkptr<4:0>
? 1999-2013 microchip technology inc. ds39026d-page 39 pic18cxx2 4.3 fast register stack a "fast interrupt return" option is available for interrupts. a fast register stack is provided for the status, wreg and bsr registers and are only one in depth. the stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. the values in the registers are then loaded back into the working regis- ters, if the fast return instruction is used to return from the interrupt. a low or high priority interrupt source will push values into the stack registers. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably for low priority interrupts. if a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority inter- rupt will be overwritten. if high priority interrupts are not disabled during low pri- ority interrupts, users must save the key registers in software during a low priority interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a fast call instruction must be executed. example 4-1 shows a source code example that uses the fast register stack. example 4-1: fast register stack code example 4.4 pcl, pclath and pclatu the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21-bits wide. the low byte is called the pcl register. this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<15:8> bits and is not directly readable or writable. updates to the pch register may be performed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits and is not directly readable or writable. updates to the pcu register may be performed through the pclatu register. the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the lsb of pcl is fixed to a value of ?0?. the pc increments by 2 to address sequential instruc- tions in the program memory. the call, rcall, goto and program branch instructions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. the contents of pclath and pclatu will be trans- ferred to the program counter by an operation that writes pcl. similarly, the upper two bytes of the pro- gram counter will be transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 4.8.1). 4.5 clocking scheme/instruction cycle the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pro- gram counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruc- tion is decoded and executed during the following q1 through q4. the clocks and instruction execution flow is shown in figure 4-4. figure 4-4: clock/ instruction cycle call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ? ? sub1 ? ? ? return fast ;restore values saved ;in fast register stack q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+2 pc+4 execute inst (pc-2) fetch inst (pc) execute inst (pc) fetch inst (pc+2) execute inst (pc+2) fetch inst (pc+4) internal phase clock
pic18cxx2 ds39026d-page 40 ? 1999-2013 microchip technology inc. 4.6 instruction flow/pipelining an ?instruction cycle? consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g. goto ), then two cycles are required to complete the instruction (example 4-2). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ?instruction register" (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). example 4-2: instruction pipeline flow 4.7 instructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb =?0?). figure 4-5 shows an example of how instruction words are stored in the pro- gram memory. to maintain alignment with instruction boundaries, the pc increments in steps of 2 and the lsb will always read ?0? (see section 4.4). the call and goto instructions have an absolute pro- gram memory address embedded into the instruction. since instructions are always stored on word bound- aries, the data contained in the instruction is a word address. the word address is written to pc<20:1>, which accesses the desired byte address in program memory. instruction #2 in figure 4-5 shows how the instruction ? goto 000006h ? is encoded in the program memory. program branch instructions, which encode a relative address offset, operate in the same manner. the offset value stored in a branch instruction repre- sents the number of single word instructions that the pc will be offset by. section 19.0 provides further details of the instruction set. figure 4-5: instructions in program memory all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ?flushed? from the pipeline, while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush ( nop ) 5. instruction @ address sub_1 fetch sub_1 execute sub_1 word address lsb = 1 lsb = 0 ? program memory byte locations ? ? 000000h 000002h 000004h 000006h instruction 1: movlw 055h 0fh 55h 000008h instruction 2: goto 000006h efh 03h 00000ah f0h 00h 00000ch instruction 3: movff 123h, 456h c1h 23h 00000eh f4h 56h 000010h 000012h 000014h
? 1999-2013 microchip technology inc. ds39026d-page 41 pic18cxx2 4.7.1 two-word instructions the pic18cxx2 devices have four two-word instruc- tions: movff, call, goto and lfsr . the second word of these instructions has the 4 msbs set to 1?s and is a special kind of nop instruction. the lower 12- bits of the second word contain data to be used by the instruction. if the first word of the instruction is exe- cuted, the data in the second word is accessed. if the second word of the instruction is executed by itself (first word was skipped), it will execute as a nop . this action is necessary when the two-word instruction is preceded by a conditional instruction that changes the pc. a pro- gram example that demonstrates this concept is shown in example 4-3. refer to section 19.0 for further details of the instruction set. example 4-3: two- word instructions 4.8 lookup tables lookup tables are implemented two ways. these are: ? computed goto ? table reads 4.8.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). a lookup table can be formed with an addwf pcl instruction and a group of retlw 0xnn instructions. wreg is loaded with an offset into the table, before executing a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruction executed will be one of the retlw 0xnn instructions that returns the value 0xnn to the calling function. the offset value (value in wreg) specifies the number of bytes that the program counter should advance. in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. 4.8.2 table reads/table writes a better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. lookup table data may be stored 2 bytes per program word by using table reads and writes. the table pointer (tblptr) specifies the byte address and the table latch (tablat) contains the data that is read from, or written to program memory. data is transferred to/from program memory one byte at a time. a description of the table read/table write operation is shown in section 5.0. case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, execute 2-word instruction 1111 0100 0101 0110 ; 2nd operand holds address of reg2 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes 1111 0100 0101 0110 ; 2nd operand becomes nop 0010 0100 0000 0000 addwf reg3 ; continue code
pic18cxx2 ds39026d-page 42 ? 1999-2013 microchip technology inc. 4.9 data memory organization the data memory is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. figure 4-6 and figure 4-7 show the data memory organization for the pic18cxx2 devices. the data memory map is divided into as many as 16 banks that contain 256 bytes each. the lower 4 bits of the bank select register (bsr<3:0>) select which bank will be accessed. the upper 4 bits for the bsr are not implemented. the data memory contains special function registers (sfr) and general purpose registers (gpr). the sfrs are used for control and status of the controller and peripheral functions, while gprs are used for data storage and scratch pad operations in the user?s appli- cation. the sfrs start at the last location of bank 15 (0xfff) and extend downwards. any remaining space beyond the sfrs in the bank may be implemented as gprs. gprs start at the first location of bank 0 and grow upwards. any read of an unimplemented location will read as ?0?s. the entire data memory may be accessed directly, or indirectly. direct addressing may require the use of the bsr register. indirect addressing requires the use of a file select register (fsrn) and corresponding indirect file operand (indfn). each fsr holds a 12-bit address value that can be used to access any location in the data memory map without banking. the instruction set and architecture allow operations across all banks. this may be accomplished by indirect addressing or by the use of the movff instruction. the movff instruction is a two-word/two-cycle instruction that moves a value from one register to another. to ensure that commonly used registers (sfrs and select gprs) can be accessed in a single cycle, regardless of the current bsr values, an access bank is implemented. a segment of bank 0 and a segment of bank 15 comprise the access ram. section 4.10 pro- vides a detailed description of the access ram. 4.9.1 general purpose register file the register file can be accessed either directly, or indi- rectly. indirect addressing operates using the file select registers (fsrn) and corresponding indirect file operand (indfn). the operation of indirect addressing is shown in section 4.12. enhanced mcu devices may have banked memory in the gpr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. data ram is available for use as gpr registers by all instructions. the top half of bank 15 (0xf80 to 0xfff) contains sfrs. all other banks of data memory contain gpr registers, starting with bank 0. 4.9.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for control- ling the desired operation of the device. these regis- ters are implemented as static ram. a list of these registers is given in table 4-1 and table 4-2. the sfrs can be classified into two sets; those asso- ciated with the ?core? function and those related to the peripheral functions. those registers related to the ?core? are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. the sfrs are typically distributed among the peripher- als whose functions they control. the unused sfr locations will be unimplemented and read as '0's. see table 4-1 for addresses for the sfrs.
? 1999-2013 microchip technology inc. ds39026d-page 43 pic18cxx2 figure 4-6: data memory map for PIC18C242/442 bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000b = 0001b = 1111b 080h 07fh f80h fffh 00h 7fh 80h ffh access bank when a = 0, the bsr is ignored and the access bank is used. the first 128 bytes are general purpose ram (from bank 0). the second 128 bytes are special function registers (from bank 15). when a = 1, the bsr is used to specify the ram location that the instruc- tion uses. f7fh f00h effh 1ffh 100h 0ffh 000h access ram ffh 00h ffh 00h ffh 00h gpr gpr sfr unused access ram high access ram low bank 2 to 200h unused read ?00h? = 1110b = 0010b (sfr?s)
pic18cxx2 ds39026d-page 44 ? 1999-2013 microchip technology inc. figure 4-7: data memory map for pic18c252/452 bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000b = 0001b = 1110b = 1111b 080h 07fh f80h fffh 00h 7fh 80h ffh access bank when a = 0, the bsr is ignored and the access bank is used. the first 128 bytes are general purpose ram (from bank 0). the second 128 bytes are special function registers (from bank 15). when a = 1, the bsr is used to specify the ram location that the instruc- tion uses. bank 4 bank 3 bank 2 f7fh f00h effh 3ffh 300h 2ffh 200h 1ffh 100h 0ffh 000h = 0110b = 0101b = 0011b = 0010b access ram ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h gpr gpr gpr gpr sfr unused access ram high access ram low bank 5 gpr gpr bank 6 to 4ffh 400h 5ffh 500h 600h unused read ?00h? = 0100b (sfr?s)
? 1999-2013 microchip technology inc. ds39026d-page 45 pic18cxx2 table 4-1: special function register map fffh tosu fdfh indf2 (3) fbfh ccpr1h f9fh ipr1 ffeh tosh fdeh postinc2 (3) fbeh ccpr1l f9eh pir1 ffdh tosl fddh postdec2 (3) fbdh ccp1con f9dh pie1 ffch stkptr fdch preinc2 (3) fbch ccpr2h f9ch ? ffbh pclatu fdbh plusw2 (3) fbbh ccpr2l f9bh ? ffah pclath fdah fsr2h fbah ccp2con f9ah ? ff9h pcl fd9h fsr2l fb9h ?f99h ? ff8h tblptru fd8h status fb8h ?f98h ? ff7h tblptrh fd7h tmr0h fb7h ?f97h ? ff6h tblptrl fd6h tmr0l fb6h ?f96htrise (2) ff5h tablat fd5h t0con fb5h ?f95htrisd (2) ff4h prodh fd4h ?fb4h ?f94htrisc ff3h prodl fd3h osccon fb3h tmr3h f93h trisb ff2h intcon fd2h lvdcon fb2h tmr3l f92h trisa ff1h intcon2 fd1h wdtcon fb1h t3con f91h ? ff0h intcon3 fd0h rcon fb0h ?f90h ? fefh indf0 (3) fcfh tmr1h fafh spbrg f8fh ? feeh postinc0 (3) fceh tmr1l faeh rcreg f8eh ? fedh postdec0 (3) fcdh t1con fadh txreg f8dh late (2) fech preinc0 (3) fcch tmr2 fach txsta f8ch latd (2) febh plusw0 (3) fcbh pr2 fabh rcsta f8bh latc feah fsr0h fcah t2con faah ?f8ahlatb fe9h fsr0l fc9h sspbuf fa9h ?f89hlata fe8h wreg fc8h sspadd fa8h ?f88h ? fe7h indf1 (3) fc7h sspstat fa7h ?f87h ? fe6h postinc1 (3) fc6h sspcon1 fa6h ?f86h ? fe5h postdec1 (3) fc5h sspcon2 fa5h ?f85h ? fe4h preinc1 (3) fc4h adresh fa4h ?f84hporte (2) fe3h plusw1 (3) fc3h adresl fa3h ?f83hportd (2) fe2h fsr1h fc2h adcon0 fa2h ipr2 f82h portc fe1h fsr1l fc1h adcon1 fa1h pir2 f81h portb fe0h bsr fc0h ?fa0hpie2f80hporta note 1: unimplemented registers are read as ?0?. 2: this register is not available on pic18c2x2 devices. 3: this is not a physical register.
pic18cxx2 ds39026d-page 46 ? 1999-2013 microchip technology inc. table 4-2: register file summary file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: tosu ? ? ? top-of-stack upper byte (tos<20:16>) ---0 0000 37 tosh top-of-stack high byte (tos<15:8>) 0000 0000 37 tosl top-of-stack low byte (tos<7:0>) 0000 0000 37 stkptr stkful stkunf ? return stack pointer 00-0 0000 38 pclatu ? ? ? holding register for pc<20:16> ---0 0000 39 pclath holding register for pc<15:8> 0000 0000 39 pcl pc low byte (pc<7:0>) 0000 0000 39 tblptru ? ?bit21 (2) program memory table pointer upper byte (tblptr<20:16>) ---0 0000 57 tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 57 tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 57 tablat program memory table latch 0000 0000 57 prodh product register high byte xxxx xxxx 61 prodl product register low byte xxxx xxxx 61 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 65 intcon2 rbpu intedg0 intedg1 intedg2 ?tmr0ip ?rbip 1111 -1-1 66 intcon3 int2ip int1ip ? int2ie int1ie ? int2if int1if 11-0 0-00 67 indf0 uses contents of fsr0 to address data memory - value of fsr0 not changed (not a physical register) n/a 50 postinc0 uses contents of fsr0 to address data memory - value of fsr0 post-incremented (not a physical register) n/a 50 postdec0 uses contents of fsr0 to address data memory - value of fsr0 post-decremented (not a physical register) n/a 50 preinc0 uses contents of fsr0 to address data memory - value of fsr0 pre-incremented (not a physical register) n/a 50 plusw0 uses contents of fsr0 to address data memory - value of fsr0 pre-incremented (not a physical register) - value of fsr0 offset by value in wreg n/a 50 fsr0h ? ? ? ? indirect data memory address pointer 0 high byte ---- 0000 50 fsr0l indirect data memory address pointer 0 low byte xxxx xxxx 50 wreg working register xxxx xxxx indf1 uses contents of fsr1 to address data memory - value of fsr1 not changed (not a physical register) n/a 50 postinc1 uses contents of fsr1 to address data memory - value of fsr1 post-incremented (not a physical register) n/a 50 postdec1 uses contents of fsr1 to address data memory - value of fsr1 post-decremented (not a physical register) n/a 50 preinc1 uses contents of fsr1 to address data memory - value of fsr1 pre-incremented (not a physical register) n/a 50 plusw1 uses contents of fsr1 to address data memory - value of fsr1 pre-incremented (not a physical register) - value of fsr1 offset by value in wreg n/a 50 fsr1h ? ? ? ? indirect data memory address pointer 1 high byte ---- 0000 50 fsr1l indirect data memory address pointer 1 low byte xxxx xxxx 50 bsr ? ? ? ? bank select register ---- 0000 49 indf2 uses contents of fsr2 to address data memory - value of fsr2 not changed (not a physical register) n/a 50 postinc2 uses contents of fsr2 to address data memory - value of fsr2 post-incremented (not a physical register) n/a 50 postdec2 uses contents of fsr2 to address data memory - value of fsr2 post-decremented (not a physical register) n/a 50 preinc2 uses contents of fsr2 to address data memory - value of fsr2 pre-incremented (not a physical register) n/a 50 plusw2 uses contents of fsr2 to address data memory - value of fsr2 pre-incremented (not a physical register) - value of fsr2 offset by value in wreg n/a 50 fsr2h ? ? ? ? indirect data memory address pointer 2 high byte ---- 0000 50 fsr2l indirect data memory address pointer 2 low byte xxxx xxxx 50 status ? ? ?novzdcc ---x xxxx 52 tmr0h timer0 register high byte 0000 0000 95 tmr0l timer0 register low byte xxxx xxxx 95 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 93 osccon ? ? ? ? ? ? ?scs ---- ---0 20 lvdcon ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 --00 0101 175 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: ra6 and associated bits are configured as port pins in rcio and ecio oscillator mode only, and read '0' in all other oscillator modes. 2: bit 21 of the tblptru allows access to the device configuration bits.
? 1999-2013 microchip technology inc. ds39026d-page 47 pic18cxx2 wdtcon ? ? ? ? ? ? ?swdte ---- ---0 183 rcon ipen lwrt ?ri to pd por bor 0q-1 11qq 53, 56, 74 tmr1h timer1 register high byte xxxx xxxx 97 tmr1l timer1 register low byte xxxx xxxx 97 t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 97 tmr2 timer2 register 0000 0000 101 pr2 timer2 period register 1111 1111 102 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 101 sspbuf ssp receive buffer/transmit register xxxx xxxx 121 sspadd ssp address register in i 2 c slave mode. ssp baud rate reload register in i 2 c master mode. 0000 0000 128 sspstat smp cke d/a psr/w ua bf 0000 0000 116 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 118 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 120 adresh a/d result register high byte xxxx xxxx 171,172 adresl a/d result register low byte xxxx xxxx 171,172 adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon 0000 00-0 165 adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 00-- 0000 166 ccpr1h capture/compare/pwm register1 high byte xxxx xxxx 111, 113 ccpr1l capture/compare/pwm register1 low byte xxxx xxxx 111, 113 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 107 ccpr2h capture/compare/pwm register2 high byte xxxx xxxx 111, 113 ccpr2l capture/compare/pwm register2 low byte xxxx xxxx 111, 113 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 107 tmr3h timer3 register high byte xxxx xxxx 103 tmr3l timer3 register low byte xxxx xxxx 103 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 103 spbrg usart1 baud rate generator 0000 0000 151 rcreg usart1 receive register 0000 0000 158, 161, 163 txreg usart1 transmit register 0000 0000 156, 159, 162 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 149 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 150 table 4-2: register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: ra6 and associated bits are configured as port pins in rcio and ecio oscillator mode only, and read '0' in all other oscillator modes. 2: bit 21 of the tblptru allows access to the device configuration bits.
pic18cxx2 ds39026d-page 48 ? 1999-2013 microchip technology inc. ipr2 ? ? ? ? bclip lvdip tmr3ip ccp2ip ---- 1111 73 pir2 ? ? ? ? bclif lvdif tmr3if ccp2if ---- 0000 69 pie2 ? ? ? ? bclie lvdie tmr3ie ccp2ie ---- 0000 71 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 72 pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 68 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 70 trise ibf obf ibov pspmode ? data direction bits for porte 0000 -111 88 trisd data direction control register for portd 1111 1111 85 trisc data direction control register for portc 1111 1111 83 trisb data direction control register for portb 1111 1111 80 trisa ? trisa6 (1) data direction control register for porta -111 1111 77 late ? ? ? ? ? read porte data latch, write porte data latch ---- -xxx 87 latd read portd data latch, write portd data latch xxxx xxxx 85 latc read portc data latch, write portc data latch xxxx xxxx 83 latb read portb data latch, write portb data latch xxxx xxxx 80 lata ?lata6 (1) read porta data latch, write porta data latch (1) -xxx xxxx 77 porte read porte pins, write porte data latch ---- -000 87 portd read portd pins, write portd data latch xxxx xxxx 85 portc read portc pins, write portc data latch xxxx xxxx 83 portb read portb pins, write portb data latch xxxx xxxx 80 porta ?ra6 (1) read porta pins, write porta data latch (1) -x0x 0000 77 table 4-2: register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: ra6 and associated bits are configured as port pins in rcio and ecio oscillator mode only, and read '0' in all other oscillator modes. 2: bit 21 of the tblptru allows access to the device configuration bits.
? 1999-2013 microchip technology inc. ds39026d-page 49 pic18cxx2 4.10 access bank the access bank is an architectural enhancement, which is very useful for c compiler code optimization. the techniques used by the c compiler may also be useful for programs written in assembly. this data memory region can be used for: ? intermediate computational values ? local variables of subroutines ? faster context saving/switching of variables ? common variables ? faster evaluation/control of sfrs (no banking) the access bank is comprised of the upper 128 bytes in bank 15 (sfrs) and the lower 128 bytes in bank 0. these two sections will be referred to as access ram high and access ram low, respectively. figure 4-6 and figure 4-7 indicate the access ram areas. a bit in the instruction word specifies if the operation is to occur in the bank specified by the bsr register or in the access bank. this bit is denoted by the ?a? bit (for access bit). when forced in the access bank (a = ?0?), the last address in access ram low is followed by the first address in access ram high. access ram high maps the special function registers, so that these registers can be accessed without any software overhead. this is useful for testing status flags and modifying control bits. 4.11 bank select register (bsr) the need for a large general purpose memory space dictates a ram banking scheme. the data memory is partitioned into sixteen banks. when using direct addressing, the bsr should be configured for the desired bank. bsr<3:0> holds the upper 4 bits of the 12-bit ram address. the bsr<7:4> bits will always read ?0?s, and writes will have no effect. a movlb instruction has been provided in the instruc- tion set to assist in selecting banks. if the currently selected bank is not implemented, any read will return all '0's and all writes are ignored. the status register bits will be set/cleared as appropriate for the instruction performed. each bank extends up to ffh (256 bytes). all data memory is implemented as static ram. a movff instruction ignores the bsr, since the 12-bit addresses are embedded into the instruction word. section 4.12 provides a description of indirect address- ing, which allows linear addressing of the entire ram space. figure 4-8: direct addressing note 1: for register file map detail, see table 4-1. 2: the access bit of the instruction can be used to force an override of the selected bank (bsr<3:0>) to the reg- isters of the access bank. 3: the movff instruction embeds the entire 12-bit address in the instruction. data memory (1) direct addressing bank select (2) location select (3) bsr<3:0> 7 0 from opcode (3) 00h 01h 0eh 0fh bank 0 bank 1 bank 14 bank 15 1ffh 100h 0ffh 000h effh e00h fffh f00h
pic18cxx2 ds39026d-page 50 ? 1999-2013 microchip technology inc. 4.12 indirect addressing, indf and fsr registers indirect addressing is a mode of addressing data mem- ory, where the data memory address in the instruction is not fixed. an fsr register is used as a pointer to the data memory location that is to be read or written. since this pointer is in ram, the contents can be modified by the program. this can be useful for data tables in the data memory and for software stacks. figure 4-9 shows the operation of indirect addressing. this shows the moving of the value to the data memory address, specified by the value of the fsr register. indirect addressing is possible by using one of the indf registers. any instruction using the indf register actually accesses the register pointed to by the file select register, fsr. reading the indf register itself, indirectly (fsr = '0'), will read 00h. writing to the indf register indirectly, results in a no operation. the fsr register contains a 12-bit address, which is shown in figure 4-10. the indfn register is not a physical register. address- ing indfn actually addresses the register whose address is contained in the fsrn register (fsrn is a pointer). this is indirect addressing. example 4-4 shows a simple use of indirect addressing to clear the ram in bank1 (locations 100h-1ffh) in a minimum number of instructions. example 4-4: how to clear ram (bank1) using indirect addressing there are three indirect addressing registers. to address the entire data memory space (4096 bytes), these registers are 12-bit wide. to store the 12-bits of addressing information, two 8-bit registers are required. these indirect addressing registers are: 1. fsr0: composed of fsr0h:fsr0l 2. fsr1: composed of fsr1h:fsr1l 3. fsr2: composed of fsr2h:fsr2l in addition, there are registers indf0, indf1 and indf2, which are not physically implemented. reading or writing to these registers activates indirect address- ing, with the value in the corresponding fsr register being the address of the data. if an instruction writes a value to indf0, the value will be written to the address pointed to by fsr0h:fsr0l. a read from indf1 reads the data from the address pointed to by fsr1h:fsr1l. indfn can be used in code anywhere an operand can be used. if indf0, indf1 or indf2 are read indirectly via an fsr, all '0's are read (zero bit is set). similarly, if indf0, indf1 or indf2 are written to indirectly, the operation will be equivalent to a nop instruction and the status bits are not affected. 4.12.1 indirect addressing operation each fsr register has an indf register associated with it, plus four additional register addresses. perform- ing an operation on one of these five registers deter- mines how the fsr will be modified during indirect addressing. when data access is done to one of the five indfn locations, the address selected will configure the fsrn register to: ? do nothing to fsrn after an indirect access (no change) - indfn ? auto-decrement fsrn after an indirect access (post-decrement) - postdecn ? auto-increment fsrn after an indirect access (post-increment) - postincn ? auto-increment fsrn before an indirect access (pre-increment) - preincn ? use the value in the wreg register as an offset to fsrn. do not modify the value of the wreg or the fsrn register after an indirect access (no change) - pluswn when using the auto-increment or auto-decrement fea- tures, the effect on the fsr is not reflected in the status register. for example, if the indirect address causes the fsr to equal '0', the z bit will not be set. incrementing or decrementing an fsr affects all 12 bits. that is, when fsrnl overflows from an increment, fsrnh will be incremented automatically. adding these features allows the fsrn to be used as a stack pointer, in addition to its uses for table operations in data memory. each fsr has an address associated with it that per- forms an indexed indirect access. when a data access to this indfn location (pluswn) occurs, the fsrn is configured to add the signed value in the wreg regis- ter and the value in fsr to form the address before an indirect access. the fsr value is not changed. if an fsr register contains a value that points to one of the indfn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a nop (status bits are not affected). lfsr fsr0, 0x100 ; next clrf postinc0 ; clear indf register ; & inc pointer btfss fsr0h, 1 ; all done w/ bank1? goto next ; no, clear next continue ; yes, continue
? 1999-2013 microchip technology inc. ds39026d-page 51 pic18cxx2 if an indirect addressing operation is done where the target address is an fsrnh or fsrnl register, the write operation will dominate over the pre- or post- increment/decrement functions. figure 4-9: indirect addressing operation figure 4-10: indirect addressing opcode address file address = access of an indirect addressing register fsr instruction executed instruction fetched ram opcode file 12 12 12 bsr<3:0> 8 4 0h fffh note 1: for register file map detail, see table 4-1. data memory (1) indirect addressing fsr register 11 0 0fffh 0000h location select
pic18cxx2 ds39026d-page 52 ? 1999-2013 microchip technology inc. 4.13 status register the status register, shown in register 4-2, contains the arithmetic status of the alu. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc, c, ov or n bits, then the write to these five bits is disabled. these bits are set or cleared according to the device logic. there- fore, the result of an instruction with the status regis- ter as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf, movff and movwf instructions are used to alter the status register, because these instructions do not affect the z, c, dc, ov or n bits from the status register. for other instructions not affecting any status bits, see table 19-2. register 4-2: status register note: the c and dc bits operate as a borrow and digit borrow bit respectively, in subtraction. u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ?novzdcc bit 7 bit 0 bit 7-5 unimplemented: read as '0' bit 4 n: negative bit this bit is used for signed arithmetic (2?s complement). it indicates whether the result was negative, (alu msb = 1). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2?s complement). it indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit7) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit for addwf, addlw, sublw , and subwf instructions 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result note: for borrow, the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. bit 0 c: carry/borrow bit for addwf, addlw, sublw , and subwf instructions 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow, the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1999-2013 microchip technology inc. ds39026d-page 53 pic18cxx2 4.13.1 rcon register the reset control (rcon) register contains flag bits that allow differentiation between the sources of a device reset. these flags include the to , pd , por , bor and ri bits. this register is readable and writable. . register 4-3: rcon register note 1: if the boren configuration bit is set (brown-out reset enabled), the bor bit is ?1? on a power-on reset. after a brown- out reset has occurred, the bor bit will be clear and must be set by firmware to indicate the occurrence of the next brown- out reset. if the boren configuration bit is clear (brown-out reset disabled), bor is unknown after power-on reset and brown-out reset conditions. 2: it is recommended that the por bit be set after a power-on reset has been detected, so that subsequent power-on resets may be detected. r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 ipen lwrt ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (16cxxx compatibility mode) bit 6 lwrt: long write enable bit 1 = enable tblwt to internal program memory once this bit is set, it can only be cleared by a por or mclr reset. 0 = disable tblwt to internal program memory; tblwt only to external program memory bit 5 unimplemented: read as '0' bit 4 ri : reset instruction flag bit 1 = the reset instruction was not executed 0 = the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog time-out flag bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18cxx2 ds39026d-page 54 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 55 pic18cxx2 5.0 table reads/table writes enhanced devices have two memory spaces: the pro- gram memory space and the data memory space. the program memory space is 16-bits wide, while the data memory space is 8 bits wide. table reads and table writes have been provided to move data between these two memory spaces through an 8-bit register (tablat). the operations that allow the processor to move data between the data and program memory spaces are: ? table read ( tblrd ) ? table write ( tblwt ) table read operations retrieve data from program memory and place it into the data memory space. figure 5-1 shows the operation of a table read with program and data memory. table write operations store data from the data mem- ory space into program memory. figure 5-2 shows the operation of a table write with program and data memory. table operations work with byte entities. a table block containing data is not required to be word aligned, so a table block can start and end at any byte address. if a table write is being used to write an executable pro- gram to program memory, program instructions will need to be word aligned. figure 5-1: table read op eration figure 5-2: table write operation table pointer (1) table latch (8-bit) program memory tblptrh tblptrl tablat tblptru instruction: tblrd * note 1: table pointer points to a byte in program memory. program memory (tblptr) table pointer (1) table latch (8-bit) program memory tblptrh tblptrl tablat program memory (tblptr) tblptru instruction: tblwt * note 1: table pointer points to a byte in program memory.
pic18cxx2 ds39026d-page 56 ? 1999-2013 microchip technology inc. 5.1 control registers several control registers are used in conjunction with the tblrd and tblwt instructions. these include the: ? tblptr registers ? tablat register ? rcon register 5.1.1 rcon register the lwrt bit specifies the operation of table writes to internal memory when the v pp voltage is applied to the mclr pin. when the lwrt bit is set, the controller continues to execute user code, but long table writes are allowed (for programming internal program mem- ory) from user mode. the lwrt bit can be cleared only by performing either a por or mclr reset. register 5-1: rcon register (address: fd0h) r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 ipen lwrt ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (16cxxx compatibility mode) bit 6 lwrt: long write enable bit 1 = enable tblwt to internal program memory 0 = disable tblwt to internal program memory. note: only cleared on a por or mclr reset. this bit has no effect on tblwts to external program memory. bit 5 unimplemented : read as '0' bit 4 ri : reset instruction flag bit 1 = no reset instruction occurred 0 = a reset instruction occurred bit 3 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset or por reset occurred 0 = a brown-out reset or por reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1999-2013 microchip technology inc. ds39026d-page 57 pic18cxx2 5.1.2 tablat - table latch register the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch is used to hold 8-bit data during data transfers between program memory and data memory. 5.1.3 tblptr - table pointer register the table pointer (tblptr) addresses a byte within the program memory. the tblptr is comprised of three sfr registers (table pointer upper byte, high byte and low byte). these three registers (tblptru:tblptrh:tblptrl) join to form a 22-bit wide pointer. the lower 21-bits allow the device to address up to 2 mbytes of program memory space. the 22nd bit allows access to the device id, the user id and the configuration bits. the table pointer, tblptr, is used by the tblrd and tblwt instructions. these instructions can update the tblptr in one of four ways, based on the table operation. these operations are shown in table 5-1. these opera- tions on the tblptr only affect the lower 21-bits. table 5-1: table pointer operations with tblrd and tblwt instructions 5.2 internal program memory read/ writes 5.2.1 table read overview ( tblrd ) the tblrd instructions are used to read data from program memory to data memory. tblptr points to a byte address in program space. executing tblrd places the byte pointed to into tab- lat. in addition, tblptr can be modified automati- cally for the next table read operation. table reads from program memory are performed one byte at a time. the instruction will load tablat with the one byte from program memory pointed to by tblptr. 5.2.2 internal program memory write block size the internal program memory of pic18cxxx devices is written in blocks. for pic18cxx2 devices, the write block size is 2 bytes. consequently, table write opera- tions to internal program memory are performed in pairs, one byte at a time. when a table write occurs to an even program mem- ory address (tblptr<0> = 0), the contents of tablat are transferred to an internal holding register. this is performed as a short write and the program memory block is not actually programmed at this time. the hold- ing register is not accessible by the user. when a table write occurs to an odd program memory address (tblptr<0>=1), a long write is started. dur- ing the long write, the contents of tablat are written to the high byte of the program memory block and the contents of the holding register are transferred to the low byte of the program memory block. figure 5-3 shows the holding register and the program memory write blocks. if a single byte is to be programmed, the low (even) byte of the destination program word should be read using tblrd *, modified or changed, if required, and written back to the same address using tblwt*+ . the high (odd) byte should be read using tblrd* , modified or changed if required, and written back to the same address using tblwt . a write to the odd address will cause a long write to begin. this process ensures that existing data in either byte will not be changed unless desired. example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write
pic18cxx2 ds39026d-page 58 ? 1999-2013 microchip technology inc. figure 5-3: holding register and the write block 5.2.2.1 operation the long write is what actually programs words of data into the internal memory. when a tblwt to the msb of the write block occurs, instruction execution is halted. during this time, programming voltage and the data stored in internal latches is applied to program memory. for a long write to occur: 1. mclr /v pp pin must be at the programming voltage 2. lwrt bit must be set 3. tblwt to the address of the msb of the write block if the lwrt bit is clear, a short write will occur and pro- gram memory will not be changed. if the tblwt is not to the msb of the write block, then the programming phase is not initiated. setting the lwrt bit enables long writes when the mclr pin is taken to v pp voltage. once the lwrt bit is set, it can be cleared only by performing a por or mclr reset. to ensure that the memory location has been well pro- grammed, a minimum programming time is required. the long write can be terminated after the program- ming time has expired by a reset or an interrupt. having only one interrupt source enabled to terminate the long write ensures that no unintended interrupts will prematurely terminate the long write. 5.2.2.2 sequence of events the sequence of events for programming an internal program memory location should be: 1. enable the interrupt that terminates the long write. disable all other interrupts. 2. clear the source interrupt flag. 3. if interrupt service routine execution is desired when the device wakes, enable global interrupts. 4. set lwrt bit in the rcon register. 5. raise mclr /v pp pin to the programming voltage, v pp . 6. clear the wdt (if enabled). 7. set the interrupt source to interrupt at the required time. 8. execute the table write for the lower (even) byte. this will be a short write. 9. execute the table write for the upper (odd) byte. this will be a long write. the microcontroller will then halt internal operations. (this is not the same as sleep mode, as the clocks and peripherals will continue to run.) the interrupt will cause the microcontroller to resume operation. 10. if gie was set, service the interrupt request. 11. lower mclr /v pp pin to v dd . 12. verify the memory location (table read). block n block n + 1 block n + 2 msb the write to the msb of the write block causes the entire block to be written to pro- gram memory. the program memory block that is written depends on the address that is written to in the msb of the write block. holding register program memory (x 2-bits) write block
? 1999-2013 microchip technology inc. ds39026d-page 59 pic18cxx2 5.2.3 interrupts the long write must be terminated by a reset or any interrupt. the interrupt source must have its interrupt enable bit set. when the source sets its interrupt flag, program- ming will terminate. this will occur, regardless of the settings of interrupt priority bits, the gie/gieh bit, or the pie/giel bit. depending on the states of interrupt priority bits, the gie/gieh bit or the pie/giel bit, program execution can either be vectored to the high or low priority inter- rupt service routine (isr), or continue execution from where programming commenced. in either case, the interrupt flag will not be cleared when programming is terminated and will need to be cleared by the software. table 5-2: long write execution, interrupt enable bits and interrupt results 5.2.4 unexpected termination of write operations if a write is terminated by an unplanned event such as loss of power, an unexpected reset, or an interrupt that was not disabled, the memory location just pro- grammed should be verified and reprogrammed if needed. gie/ gieh pie/ giel priority interrupt enable interrupt flag action xx x 0 (default) x long write continues even if interrupt flag becomes set. xx x 1 0 long write continues, will resume operations when the interrupt flag is set. 0 (default) 0 (default) x11 terminates long write, executes next instruction. interrupt flag not cleared. 0 (default) 1 1 high priority (default) 11 terminates long write, executes next instruction. interrupt flag not cleared. 1 0 (default) 0 low 11 terminates long write, executes next instruction. interrupt flag not cleared. 0 (default) 1 0 low 11 terminates long write, branches to low priority interrupt vector. interrupt flag can be cleared by isr. 1 0 (default) 1 high priority (default) 11 terminates long write, branches to high priority interrupt vector. interrupt flag can be cleared by isr.
pic18cxx2 ds39026d-page 60 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 61 pic18cxx2 6.0 8 x 8 hardware multiplier 6.1 introduction an 8 x 8 hardware multiplier is included in the alu of the pic18cxx2 devices. by making the multiply a hardware operation, it completes in a single instruction cycle. this is an unsigned multiply that gives a 16-bit result. the result is stored into the 16-bit product regis- ter pair (prodh:prodl). the multiplier does not affect any flags in the alusta register. making the 8 x 8 multiplier execute in a single cycle gives the following advantages: ? higher computational throughput ? reduces code size requirements for multiply algorithms the performance increase allows the device to be used in applications previously reserved for digital signal processors. table 6-1 shows a performance comparison between enhanced devices using the single cycle hardware mul- tiply, and performing the same function without the hardware multiply. table 6-1: performance comparison 6.2 operation example 6-1 shows the sequence to do an 8 x 8 unsigned multiply. only one instruction is required when one argument of the multiply is already loaded in the wreg register. example 6-2 shows the sequence to do an 8 x 8 signed multiply. to account for the sign bits of the arguments, each argument?s most significant bit (msb) is tested and the appropriate subtractions are done. example 6-1: 8 x 8 unsigned multiply routine example 6-2: 8 x 8 signed multiply routine example 6-3 shows the sequence to do a 16 x 16 unsigned multiply. equation 6-1 shows the algorithm that is used. the 32-bit result is stored in four registers, res3:res0. equation 6-1: 16 x 16 unsigned multiplication algorithm res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 )+ (arg1h ? arg2l ? 2 8 )+ (arg1l ? arg2h ? 2 8 )+ (arg1l ? arg2l) routine multiply method program memory (words) cycles (max) time @ 40 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 6.9 ? s27.6 ? s69 ? s hardware multiply 1 1 100 ns 400 ns 1 ? s 8 x 8 signed without hardware multiply 33 91 9.1 ? s36.4 ? s91 ? s hardware multiply 6 6 600 ns 2.4 ? s6 ? s 16 x 16 unsigned without hardware multiply 21 242 24.2 ? s96.8 ? s242 ? s hardware multiply 24 24 2.4 ? s9.6 ? s24 ? s 16 x 16 signed without hardware multiply 52 254 25.4 ? s 102.6 ? s254 ? s hardware multiply 36 36 3.6 ? s14.4 ? s36 ? s movf arg1, w ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movf arg1, w mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movf arg2, w btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2
pic18cxx2 ds39026d-page 62 ? 1999-2013 microchip technology inc. example 6-3: 16 x 16 unsigned multiply routine example 6-4 shows the sequence to do a 16 x 16 signed multiply. equation 6-2 shows the algorithm used. the 32-bit result is stored in four registers, res3:res0. to account for the sign bits of the argu- ments, each argument pairs? most significant bit (msb) is tested and the appropriate subtractions are done. equation 6-2: 16 x 16 signed multiplication algorithm res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 )+ (arg1h ? arg2l ? 2 8 )+ (arg1l ? arg2h ? 2 8 )+ (arg1l ? arg2l)+ (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 )+ (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 ) example 6-4: 16 x 16 signed multiply routine movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg, f ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg, f ; addwfc res3, f ; movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg, f ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg, f ; addwfc res3, f ; ; btfss arg2h, 7 ; arg2h:arg2l neg? bra sign_arg1 ; no, check arg1 movf arg1l, w ; subwf res2 ; movf arg1h, w ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? bra cont_code ; no, done movf arg2l, w ; subwf res2 ; movf arg2h, w ; subwfb res3 ; cont_code :
? 1999-2013 microchip technology inc. ds39026d-page 63 pic18cxx2 7.0 interrupts the pic18cxx2 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level, or a low priority level. the high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. high priority interrupt events will over- ride any low priority interrupts that may be in progress. there are ten registers which are used to control inter- rupt operation. these registers are: ? rcon ?intcon ? intcon2 ? intcon3 ? pir1, pir2 ? pie1, pie2 ? ipr1, ipr2 it is recommended that the microchip header files sup- plied with mplab ? ide be used for the symbolic bit names in these registers. this allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. each interrupt source has three bits to control its oper- ation. the functions of these bits are: ? flag bit to indicate that an interrupt event occurred ? enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set ? priority bit to select high priority or low priority the interrupt priority feature is enabled by setting the ipen bit (rcon<7>). when interrupt priority is enabled, there are two bits which enable interrupts glo- bally. setting the gieh bit (intcon<7>) enables all interrupts that have the priority bit set. setting the giel bit (intcon<6>) enables all interrupts that have the priority bit cleared. when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. individual interrupts can be disabled through their corresponding enable bits. when the ipen bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are com- patible with pic ? mid-range devices. in compatibility mode, the interrupt priority bits for each source have no effect. intcon<6> is the peie bit, which enables/dis- ables all peripheral interrupt sources. intcon<7> is the gie bit, which enables/disables all interrupt sources. all interrupts branch to address 000008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt priority levels are used, this will be either the gieh, or giel bit. high priority interrupt sources can interrupt a low prior- ity interrupt. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (000008h or 000018h). once in the interrupt service routine, the source(s) of the interrupt can be deter- mined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. the ?return from interrupt? instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel if priority levels are used), which re-enables interrupts. for external interrupt events, such as the int pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or two-cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the gie bit.
pic18cxx2 ds39026d-page 64 ? 1999-2013 microchip technology inc. figure 7-1: interrupt logic tmr0ie gieh/gie giel/peie wake-up if in sleep mode interrupt to cpu vector to location 0008h int2if int2ie int2ip int1if int1ie int1ip tmr0if tmr0ie tmr0ip int0if int0ie rbif rbie rbip ipen tmr0if tmr0ip int1if int1ie int1ip int2if int2ie int2ip rbif rbie rbip int0if int0ie giel\peie interrupt to cpu vector to location ipen ipe 0018h peripheral interrupt flag bit peripheral interrupt enable bit peripheral interrupt priority bit peripheral interrupt flag bit peripheral interrupt enable bit peripheral interrupt priority bit tmr1if tmr1ie tmr1ip xxxxif xxxxie xxxxip additional peripheral interrupts tmr1if tmr1ie tmr1ip high priority interrupt generation low priority interrupt generation xxxxif xxxxie xxxxip additional peripheral interrupts
? 1999-2013 microchip technology inc. ds39026d-page 65 pic18cxx2 7.1 intcon registers the intcon registers are readable and writable reg- isters, which contains various enable, priority, and flag bits. register 7-1: intcon register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif bit 7 bit 0 bit 7 gie/gieh: global interrupt enable bit when ipen = 0: 1 = enables all unmasked interrupts 0 = disables all interrupts when ipen = 1: 1 = enables all high priority interrupts 0 = disables all high priority interrupts bit 6 peie/giel: peripheral interrupt enable bit when ipen = 0: 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts when ipen = 1: 1 = enables all low priority peripheral interrupts 0 = disables all low priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt occurred (must be cleared in software) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
pic18cxx2 ds39026d-page 66 ? 1999-2013 microchip technology inc. register 7-2: intcon2 register r/w-1 r/w-1 r/w-1 r/w-1 u-0 r/w-1 u-0 r/w-1 rbpu intedg0 intedg1 intedg2 ?tmr0ip ?rbip bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0 :external interrupt0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1 : external interrupt1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4 intedg2 : external interrupt2 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 3 unimplemented: read as '0' bit 2 tmr0ip : tmr0 overflow interrupt priority bit 1 = high priority 0 = low priority bit 1 unimplemented: read as '0' bit 0 rbip : rb port change interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
? 1999-2013 microchip technology inc. ds39026d-page 67 pic18cxx2 register 7-3: intcon3 register r/w-1 r/w-1 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 int2ip int1ip ? int2ie int1ie ? int2if int1if bit 7 bit 0 bit 7 int2ip: int2 external interrupt priority bit 1 = high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 = high priority 0 = low priority bit 5 unimplemented: read as '0' bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 unimplemented: read as '0' bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared in software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared in software) 0 = the int1 external interrupt did not occur legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
pic18cxx2 ds39026d-page 68 ? 1999-2013 microchip technology inc. 7.2 pir registers the pir registers contain the individual flag bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are two peripheral interrupt flag registers (pir1, pir2). register 7-4: peripheral interrupt request ( flag) register 1 (pir1) note 1: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, gie (intcon<7>). 2: user software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt. r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif adif rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 pspif: parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6 adif : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rcif : usart receive interrupt flag bit 1 = the usart receive buffer, rcreg, is full (cleared when rcreg is read) 0 = the usart receive buffer is empty bit 4 txif : usart transmit interrupt flag bit 1 = the usart transmit buffer, txreg, is empty (cleared when txreg is written) 0 = the usart transmit buffer is full bit 3 sspif : master synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 ccp1if : ccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = mr1 register did not overflow legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1999-2013 microchip technology inc. ds39026d-page 69 pic18cxx2 register 7-5: peripheral interrupt request (flag) register 2 (pir2) u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? bclif lvdif tmr3if ccp2if bit 7 bit 0 bit 7-4 unimplemented: read as '0' bit 3 bclif : bus collision interrupt flag bit 1 = a bus collision occurred (must be cleared in software) 0 = no bus collision occurred bit 2 lvdif : low voltage detect interrupt flag bit 1 = a low voltage condition occurred (must be cleared in software) 0 = the device voltage is above the low voltage detect trip point bit 1 tmr3if : tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared in software) 0 = tmr3 register did not overflow bit 0 ccp2if : ccpx interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18cxx2 ds39026d-page 70 ? 1999-2013 microchip technology inc. 7.3 pie registers the pie registers contain the individual enable bits for the peripheral interrupts. due to the number of periph- eral interrupt sources, there are two peripheral inter- rupt enable registers (pie1, pie2). when ipen = 0, the peie bit must be set to enable any of these periph- eral interrupts. register 7-6: peripheral interrupt enable register 1 (pie1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 pspie: parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6 adie : a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 sspie : master synchronous serial port interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1999-2013 microchip technology inc. ds39026d-page 71 pic18cxx2 register 7-7: peripheral interrupt enable register 2 (pie2) u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? bclie lvdie tmr3ie ccp2ie bit 7 bit 0 bit 7-4 unimplemented: read as '0' bit 3 bclie : bus collision interrupt enable bit 1 = enabled 0 = disabled bit 2 lvdie : low voltage detect interrupt enable bit 1 = enabled 0 = disabled bit 1 tmr3ie : tmr3 overflow interrupt enable bit 1 = enables the tmr3 overflow interrupt 0 = disables the tmr3 overflow interrupt bit 0 ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18cxx2 ds39026d-page 72 ? 1999-2013 microchip technology inc. 7.4 ipr registers the ipr registers contain the individual priority bits for the peripheral interrupts. due to the number of periph- eral interrupt sources, there are two peripheral inter- rupt priority registers (ipr1, ipr2). the operation of the priority bits requires that the interrupt priority enable (ipen) bit be set. register 7-8: peripheral interrupt priority register 1 (ipr1) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip bit 7 bit 0 bit 7 pspip: parallel slave port read/write interrupt priority bit 1 = high priority 0 = low priority bit 6 adip : a/d converter interrupt priority bit 1 = high priority 0 = low priority bit 5 rcip : usart receive interrupt priority bit 1 = high priority 0 = low priority bit 4 txip : usart transmit interrupt priority bit 1 = high priority 0 = low priority bit 3 sspip : master synchronous serial port interrupt priority bit 1 = high priority 0 = low priority bit 2 ccp1ip : ccp1 interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr2ip : tmr2 to pr2 match interrupt priority bit 1 = high priority 0 = low priority bit 0 tmr1ip : tmr1 overflow interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1999-2013 microchip technology inc. ds39026d-page 73 pic18cxx2 register 7-9: peripheral interrupt priority regist er 2 (ipr2) u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ? bclip lvdip tmr3ip ccp2ip bit 7 bit 0 bit 7-4 unimplemented: read as '0' bit 3 bclip : bus collision interrupt priority bit 1 = high priority 0 = low priority bit 2 lvdip : low voltage detect interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr3ip : tmr3 overflow interrupt priority bit 1 = high priority 0 = low priority bit 0 ccp2ip : ccp2 interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18cxx2 ds39026d-page 74 ? 1999-2013 microchip technology inc. 7.5 rcon register the rcon register contains the bit which is used to enable prioritized interrupts (ipen). register 7-10: rcon register r/w-0 r/w-0 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen lwrt ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (16cxxx compatibility mode) bit 6 lwrt: long write enable bit for details of bit operation, see register 4-3 bit 5 unimplemented: read as '0' bit 4 ri : reset instruction flag bit for details of bit operation, see register 4-3 bit 3 to : watchdog time-out flag bit for details of bit operation, see register 4-3 bit 2 pd : power-down detection flag bit for details of bit operation, see register 4-3 bit 1 por : power-on reset status bit for details of bit operation, see register 4-3 bit 0 bor : brown-out reset status bit for details of bit operation, see register 4-3 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1999-2013 microchip technology inc. ds39026d-page 75 pic18cxx2 7.6 int0 interrupt external interrupts on the rb0/int0, rb1/int1 and rb2/int2 pins are edge triggered: either rising, if the corresponding intedgx bit is set in the intcon2 reg- ister, or falling, if the intedgx bit is clear. when a valid edge appears on the rbx/intx pin, the corresponding flag bit intxf is set. this interrupt can be disabled by clearing the corresponding enable bit intxe. flag bit intxf must be cleared in software in the interrupt ser- vice routine before re-enabling the interrupt. all exter- nal interrupts (int0, int1 and int2) can wake-up the processor from sleep, if bit intxe was set prior to going into sleep. if the global interrupt enable bit gie set, the processor will branch to the interrupt vector following wake-up. interrupt priority for int1 and int2 is determined by the value contained in the interrupt priority bits, int1ip (intcon3<6>) and int2ip (intcon3<7>). there is no priority bit associated with int0. it is always a high priority interrupt source. 7.7 tmr0 interrupt in 8-bit mode (which is the default), an overflow (ffh ? 00h) in the tmr0 register will set flag bit tmr0if. in 16-bit mode, an overflow (ffffh ?? 0000h) in the tmr0h:tmr0l registers will set flag bit tmr0if. the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>). interrupt priority for timer0 is determined by the value contained in the interrupt priority bit tmr0ip (intcon2<2>). see sec- tion 8.0 for further details on the timer0 module. 7.8 portb interrupt-on-change an input change on portb<7:4> sets flag bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit, rbie (intcon<3>). interrupt priority for portb interrupt-on-change is determined by the value contained in the interrupt pri- ority bit, rbip (intcon2<0>). 7.9 context saving during interrupts during an interrupt, the return pc value is saved on the stack. additionally, the wreg, status and bsr regis- ters are saved on the fast return stack. if a fast return from interrupt is not used (see section 4.3), the user may need to save the wreg, status and bsr regis- ters in software. depending on the user?s application, other registers may also need to be saved. example 7-1 saves and restores the wreg, status and bsr regis- ters during an interrupt service routine. example 7-1: saving status, wreg and bsr registers in ram movwf w_temp ; w_temp is in virtual bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status
pic18cxx2 ds39026d-page 76 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 77 pic18cxx2 8.0 i/o ports depending on the device selected, there are either five ports, or three ports available. some pins of the i/o ports are multiplexed with an alternate function from the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has three registers for its operation. these registers are: ? tris register (data direction register) ? port register (reads the levels on the pins of the device) ? lat register (output latch) the data latch (lat register) is useful for read-modify- write operations on the value that the i/o pins are driving. 8.1 porta, trisa and lata registers porta is a 6-bit wide, bi-directional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisa bit (= 0) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. the data latch register (lata) is also memory mapped. read-modify-write operations on the lata register reads and writes the latched output value for porta. the ra4 pin is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/ t0cki pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. the other porta pins are multiplexed with analog inputs and the analog v ref + and v ref - inputs. the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 8-1: initiali zing porta figure 8-1: block diagram of ra3:ra0 and ra5 pins note: on a power-on reset, these pins are con- figured as digital inputs. note: on a power-on reset, these pins are con- figured as analog inputs and read as '0'. clrf porta ; initialize porta by ; clearing output ; data latches clrf lata ; alternate method ; to clear output ; data latches movlw 0x07 ; configure a/d movwf adcon1 ; for digital inputs movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs data bus q d q ck q d q ck qd en p n wr lata wr trisa data latch tris latch rd trisa rd porta v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode ttl input buffer to a/d converter and lvd modules rd lata or porta ss input (ra5 only)
pic18cxx2 ds39026d-page 78 ? 1999-2013 microchip technology inc. figure 8-2: blo ck diagram of ra4/t0cki pin figure 8-3: block di agram of ra6 data bus wr trisa rd porta data latch tris latch rd trisa schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input q d q ck q d q ck en qd en rd lata wr lata or porta note 1: i/o pins have protection diodes to v dd and v ss . data bus q d q ck q d q ck qd en p n wr lata wr data latch tris latch rd trisa rd porta v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . or porta rd lata ecra6 or data bus ecra6 or enable data bus ttl input buffer rcra6 rcra6 enable trisa
? 1999-2013 microchip technology inc. ds39026d-page 79 pic18cxx2 table 8-1: porta functions table 8-2: summary of registers associated with porta name bit# buffer function ra0/an0 bit0 ttl input/output or analog input. ra1/an1 bit1 ttl input/output or analog input. ra2/an2/v ref - bit2 ttl input/output or analog input or v ref -. ra3/an3/v ref + bit3 ttl input/output or analog input or v ref +. ra4/t0cki bit4 st input/output or external clock input for timer0. output is open drain type. ra5/ss/ an4/lvdin bit5 ttl input/output or slave select input for synchronous serial port or analog input, or low voltage detect input. osc2/clko/ra6 bit6 ttl osc2 or clock output or i/o pin. legend: ttl = ttl input, st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets porta ? ra6 ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 lata ? latch a data output register --xx xxxx --uu uuuu trisa ? porta data direction register --11 1111 --11 1111 adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 --0- 0000 --0- 0000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta.
pic18cxx2 ds39026d-page 80 ? 1999-2013 microchip technology inc. 8.2 portb, trisb and latb registers portb is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisb bit (= 0) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latb) is also memory mapped. read-modify-write operations on the latb register reads and writes the latched output value for portb. example 8-2: initializing portb each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (intcon2<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are dis- abled on a power-on reset. four of the portb pins, rb7:rb4, have an interrupt- on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt- on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are or?ed together to generate the rb port change interrupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with the movff instruction). this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. rb3 can be configured by the configuration bit ccp2mx as the alternate peripheral pin for the ccp2 module (ccp2mx = ?0?). figure 8-4: block diagram of rb7:rb4 pins note: on a power-on reset, these pins are con- figured as digital inputs. clrf portb ; initialize portb by ; clearing output ; data latches clrf latb ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs data latch from other rbpu (2) p v dd i/o q d ck q d ck qd en qd en data bus wr latb wr trisb set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch ttl input buffer pin (1) st buffer rbx/intx q3 q1 rd latb or portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>).
? 1999-2013 microchip technology inc. ds39026d-page 81 pic18cxx2 figure 8-5: block di agram of rb2:rb0 pins figure 8-6: block diagram of rb3 data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). data latch p v dd q d ck q d en data bus wr latb or wr trisb rd trisb rd portb weak pull-up ccp2 input (3) ttl input buffer schmitt trigger buffer tris latch rd latb wr portb rbpu (2) ck d enable ccp output (3) rd portb ccp output (3) 1 0 p n v dd v ss i/o pin (1) q ccp2mx ccp2mx = 0 note 1: i/o pin has diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate ddr bit(s) and clear the rbpu bit (intcon2<7>). 3: the ccp2 input/output is multiplexed with rb3, if the ccp2mx bit is enabled (=?0?) in the configuration register.
pic18cxx2 ds39026d-page 82 ? 1999-2013 microchip technology inc. table 8-3: portb functions table 8-4: summary of registers associated with portb name bit# buffer function rb0/int0 bit0 ttl/st (1) input/output pin or external interrupt input1. internal software programmable weak pull-up. rb1/int1 bit1 ttl/st (1) input/output pin or external interrupt input2. internal software programmable weak pull-up. rb2/int2 bit2 ttl/st (1) input/output pin or external interrupt input3. internal software programmable weak pull-up. rb3/ccp2 (3) bit3 ttl/st (4) input/output pin. capture2 input/compare2 output/pwm output when ccp2mx configuration bit is enabled. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming clock. rb7 bit7 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: a device configuration bit selects which i/o pin the ccp2 pin is multiplexed on. 4: this buffer is a schmitt trigger input when configured as the ccp2 input. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu latb latb data output register trisb portb data direction register 1111 1111 1111 1111 intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u intcon2 rbpu intedg0 intedg1 intedg2 ? tmr0ip ? rbip 1111 -1-1 1111 -1-1 intcon3 int2ip int1ip ? int2ie int1ie ? int2if int1if 11-0 0-00 11-0 0-00 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
? 1999-2013 microchip technology inc. ds39026d-page 83 pic18cxx2 8.3 portc, trisc and latc registers portc is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisc. setting a trisc bit (= 1) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisc bit (= 0) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latc) is also memory mapped. read-modify-write operations on the latc register reads and writes the latched output value for portc. portc is multiplexed with several peripheral functions (table 8-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. the user should refer to the correspond- ing peripheral section for the correct tris bit settings. the pin override value is not loaded into the tris reg- ister. this allows read-modify-write of the tris register, without concern due to peripheral overrides. rc1 is normally configured by the configuration bit ccp2mx as the default peripheral pin for the ccp2 module (default/erased state, ccp2mx = ?1?). example 8-3: initializing portc figure 8-7: portc block di agram (peripheral output override) note: on a power-on reset, these pins are con- figured as digital inputs. clrf portc ; initialize portc by ; clearing output ; data latches clrf latc ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs data bus wr latc or wr trisc rd trisc q d q ck q d en peripheral data out 0 1 q d q ck rd portc peripheral data in wr portc rd latc peripheral output schmitt port/peripheral select (2) enable (3) p n v ss v dd i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data (input) and peripheral output. 3: peripheral output enable is only active if peripheral select is active. data latch ddr latch trigger
pic18cxx2 ds39026d-page 84 ? 1999-2013 microchip technology inc. table 8-5: portc functions table 8-6: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t1cki bit0 st input/output port pin or timer1 oscillator output/timer1 clock input. rc1/t1osi/ccp2 bit1 st input/output port pin, timer1 oscillator input, or capture2 input/ compare2 output/pwm output when ccp2mx configuration bit is disabled. rc2/ccp1 bit2 st input/output port pin or capture1 input/compare1 output/ pwm1 output. rc3/sck/scl bit3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output port pin or synchronous serial port data output. rc6/tx/ck bit6 st input/output port pin, addressable usart asynchronous transmit, or addressable usart synchronous clock. rc7/rx/dt bit7 st input/output port pin, addressable usart asynchronous receive, or addressable usart synchronous data. legend: st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu latc latc data output register xxxx xxxx uuuu uuuu trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged
? 1999-2013 microchip technology inc. ds39026d-page 85 pic18cxx2 8.4 portd, trisd and latd registers this section is only applicable to the pic18c4x2 devices. portd is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisd. setting a trisd bit (= 1) will make the corresponding portd pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisd bit (= 0) will make the corresponding portd pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latd) is also memory mapped. read-modify-write operations on the latd register reads and writes the latched output value for portd. portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually configurable as an input or output. portd can be configured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit pspmode (trise<4>). in this mode, the input buffers are ttl. see section 8.6 for additional information on the parallel slave port (psp). example 8-4: initializing portd figure 8-8: port d block diagram in i/o port mode note: on a power-on reset, these pins are con- figured as digital inputs. clrf portd ; initialize portd by ; clearing output ; data latches clrf latd ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisd ; set rd<3:0> as inputs ; rd<5:4> as outputs ; rd<7:6> as inputs data bus wr latd wr trisd rd portd data latch tris latch rd trisd schmitt trigger input buffer i/o pin (1) q d ck q d ck en qd en rd latd or portd note 1: i/o pins have diode protection to v dd and v ss .
pic18cxx2 ds39026d-page 86 ? 1999-2013 microchip technology inc. table 8-7: portd functions table 8-8: summary of registers associated with portd name bit# buffer type function rd0/psp0 bit0 st/ttl (1) input/output port pin or parallel slave port bit0. rd1/psp1 bit1 st/ttl (1) input/output port pin or parallel slave port bit1. rd2/psp2 bit2 st/ttl (1) input/output port pin or parallel slave port bit2. rd3/psp3 bit3 st/ttl (1) input/output port pin or parallel slave port bit3. rd4/psp4 bit4 st/ttl (1) input/output port pin or parallel slave port bit4. rd5/psp5 bit5 st/ttl (1) input/output port pin or parallel slave port bit5. rd6/psp6 bit6 st/ttl (1) input/output port pin or parallel slave port bit6. rd7/psp7 bit7 st/ttl (1) input/output port pin or parallel slave port bit7. legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu latd latd data output register xxxx xxxx uuuu uuuu trisd portd data direction register 1111 1111 1111 1111 trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by portd.
? 1999-2013 microchip technology inc. ds39026d-page 87 pic18cxx2 8.5 porte, trise and late registers this section is only applicable to the pic18c4x2 devices. porte is a 3-bit wide, bi-directional port. the corre- sponding data direction register is trise. setting a trise bit (= 1) will make the corresponding porte pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trise bit (= 0) will make the corresponding porte pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (late) is also memory mapped. read-modify-write operations on the late register reads and writes the latched output value for porte. porte has three pins (re0/rd /an5, re1/wr /an6 and re2/cs /an7), which are individually configurable as inputs or outputs. these pins have schmitt trigger input buffers. register 8-1 shows the trise register, which also con- trols the parallel slave port operation. porte pins are multiplexed with analog inputs. when selected as an analog input, these pins will read as '0's. trise controls the direction of the re pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. example 8-5: initializing porte figure 8-9: porte bl ock diagram in i/o port mode note: on a power-on reset, these pins are con- figured as digital inputs. note: on a power-on reset, these pins are con- figured as analog inputs. clrf porte ; initialize porte by ; clearing output ; data latches clrf late ; alternate method ; to clear output ; data latches movlw 0x07 ; configure a/d movwf adcon1 ; for digital inputs movlw 0x03 ; value used to ; initialize data ; direction movwf trisc ; set re<0> as inputs ; re<1> as outputs ; re<2> as inputs data bus wr late wr trise rd porte data latch tris latch rd trise schmitt trigger input buffer q d ck q d ck en qd en i/o pin (1) rd late or porte to analog converter note 1: i/o pins have diode protection to v dd and v ss .
pic18cxx2 ds39026d-page 88 ? 1999-2013 microchip technology inc. register 8-1: trise register r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode ? trise2 trise1 trise0 bit 7 bit 0 bit 7 ibf: input buffer full status bit 1 = a word has been received and waiting to be read by the cpu 0 = no word has been received bit 6 obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov : input buffer overflow detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3 unimplemented: read as '0' bit 2 trise2 : re2 direction control bit 1 = input 0 = output bit 1 trise1 : re1 direction control bit 1 = input 0 = output bit 0 trise0 : re0 direction control bit 1 = input 0 = output legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1999-2013 microchip technology inc. ds39026d-page 89 pic18cxx2 table 8-9: porte functions table 8-10: summary of registers associated with porte name bit# buffer type function re0/rd /an5 bit0 st/ttl (1) input/output port pin or read control input in parallel slave port mode or analog input: rd 1 = not a read operation 0 = read operation. reads portd register (if chip selected). re1/wr /an6 bit1 st/ttl (1) input/output port pin or write control input in parallel slave port mode or analog input: wr 1 = not a write operation 0 = write operation. writes portd register (if chip selected). re2/cs /an7 bit2 st/ttl (1) input/output port pin or chip select control input in parallel slave port mode or analog input: cs 1 = device is not selected 0 = device is selected legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets porte ? ? ? ? ?re2re1re0 ---- -000 ---- -000 late ? ? ? ? ? late data output register ---- -xxx ---- -uuu trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 --0- -000 --0- -000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. s haded cells are not used by porte.
pic18cxx2 ds39026d-page 90 ? 1999-2013 microchip technology inc. 8.6 parallel slave port the parallel slave port is implemented on the 40-pin devices only (pic18c4x2). portd operates as an 8-bit wide, parallel slave port, or microprocessor port, when control bit pspmode (trise<4>) is set. it is asynchronously readable and writable by the external world through rd control input pin re0/rd and wr control input pin re1/wr . it can directly interface to an 8-bit microprocessor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd to be the rd input, re1/wr to be the wr input and re2/cs to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set). the a/d port config- uration bits pcfg2:pcfg0 (adcon1<2:0>) must be set, which will configure pins re2:re0 as digital i/o. a write to the psp occurs when both the cs and wr lines are first detected low. a read from the psp occurs when both the cs and rd lines are first detected low. the porte i/o pins become control inputs for the microprocessor port when bit pspmode (trise<4>) is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are configured as digital inputs), and the adcon1 is configured for digital i/o. in this mode, the input buffers are ttl. figure 8-10: portd and porte block diagram (parallel slave port) figure 8-11: parallel slave port write waveforms data bus wr latd rdx q d ck en qd en rd portd pin one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr note: i/o pin has protection diodes to v dd and v ss . ttl ttl ttl ttl or portd rd latd data latch q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0>
? 1999-2013 microchip technology inc. ds39026d-page 91 pic18cxx2 figure 8-12: parallel slave port read waveforms table 8-11: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0> name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portd port data latch when written; port pins when read xxxx xxxx uuuu uuuu latd latd data output bits xxxx xxxx uuuu uuuu trisd portd data direction bits 1111 1111 1111 1111 porte ? ? ? ? ?re2re1re0 ---- -000 ---- -000 late ? ? ? ? ? late data output bits ---- -xxx ---- -uuu trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 intcon gie/ gieh peie/ giel tmr0if int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 --0- -000 --0- -000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells ar e not used by the parallel slave port.
pic18cxx2 ds39026d-page 92 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 93 pic18cxx2 9.0 timer0 module the timer0 module has the following features: ? software selectable as an 8-bit or 16-bit timer/ counter ? readable and writable ? dedicated 8-bit software programmable prescaler ? clock source selectable to be external or internal ? interrupt-on-overflow from ffh to 00h in 8-bit mode and ffffh to 0000h in 16-bit mode ? edge select for external clock figure 9-1 shows a simplified block diagram of the timer0 module in 8-bit mode and figure 9-2 shows a simplified block diagram of the timer0 module in 16-bit mode. the t0con register (register 9-1) is a readable and writable register that controls all the aspects of timer0, including the prescale selection. register 9-1: t0con: timer0 control register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit : timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2:0 t0ps2:t0ps0 : timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18cxx2 ds39026d-page 94 ? 1999-2013 microchip technology inc. figure 9-1: timer0 block di agram in 8-bit mode figure 9-2: timer0 block diagram in 16-bit mode note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. ra4/t0cki t0se 0 1 0 1 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 (2 t cy delay) data bus 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. t0cki pin t0se 0 1 0 1 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) data bus<7:0> 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l
? 1999-2013 microchip technology inc. ds39026d-page 95 pic18cxx2 9.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing the t0cs bit. in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0 regis- ter is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit. in counter mode, timer0 will increment either on every rising, or falling edge of pin ra4/t0cki. the increment- ing edge is determined by the timer0 source edge select bit (t0se). clearing the t0se bit selects the ris- ing edge. restrictions on the external clock input are discussed below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 9.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not readable or writable. the psa and t0ps2:t0ps0 bits determine the pres- caler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf tmr0, movwf tmr0, bsf tmr0, x ....etc.) will clear the prescaler count. 9.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol (i.e., it can be changed ?on-the-fly? during program execution). 9.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h in 8-bit mode, or ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if bit. the interrupt can be masked by clearing the tmr0ie bit. the tmr0ie bit must be cleared in soft- ware by the timer0 module interrupt service routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep, since the timer is shut-off during sleep. 9.4 16-bit mode timer reads and writes tmr0h is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of timer0 (refer to figure 9-2). the high byte of the timer0 counter/timer is not directly readable nor writable. tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this pro- vides the ability to read all 16-bits of timer0 without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte. a write to the high byte of timer0 must also take place through the tmr0h buffer register. timer0 high byte is updated with the contents of tmr0h when a write occurs to tmr0l. this allows all 16-bits of timer0 to be updated at once. table 9-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets tmr0l timer0 module?s low byte register xxxx xxxx uuuu uuuu tmr0h timer0 module?s high byte register 0000 0000 0000 0000 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 1111 1111 trisa ? ? porta data direction register --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0.
pic18cxx2 ds39026d-page 96 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 97 pic18cxx2 10.0 timer1 module the timer1 module timer/counter has the following features: ? 16-bit timer/counter (two 8-bit registers: tmr1h and tmr1l) ? readable and writable (both registers) ? internal or external clock select ? interrupt-on-overflow from ffffh to 0000h ? reset from ccp module special event trigger figure 10-1 is a simplified block diagram of the timer1 module. register 10-1 details the timer1 control register. this register controls the operating mode of the timer1 module, and contains the timer1 oscillator enable bit (t1oscen). timer1 can be enabled or disabled by set- ting or clearing control bit tmr1on (t1con<0>). register 10-1: t1con: timer1 control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1 in one 16-bit operation 0 = enables register read/write of timer1 in two 8-bit operations bit 6 unimplemented: read as '0' bit 5-4 t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable bit 1 = timer1 oscillator is enabled 0 = timer1 oscillator is shut-off the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1: 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0: this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t13cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18cxx2 ds39026d-page 98 ? 1999-2013 microchip technology inc. 10.1 timer1 operation timer1 can operate in one of these modes: ?as a timer ? as a synchronous counter ? as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). when tmr1cs = 0, timer1 increments every instruc- tion cycle. when tmr1cs = 1, timer1 increments on every rising edge of the external clock input or the timer1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. timer1 also has an internal ?reset input?. this reset can be generated by the ccp module (section 13.0). figure 10-1: timer1 block diagram figure 10-2: timer1 block diag ram: 16-bit read/write mode tmr1h tmr1l t1sync tmr1cs t1ckps1:t1ckps0 sleep input f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 tmr1if overflow tmr1 clr ccp special event trigger t1oscen enable oscillator ( 1 ) t1osc interrupt flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. t1osi t1cki/t1oso timer 1 tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) tmr1if overflow interrupt f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t13cki/t1oso t1osi tmr1 flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. th is eliminates power drain. high byte data bus<7:0> 8 tmr1h 8 8 8 read tmr1l write tmr1l clr ccp special event trigger
? 1999-2013 microchip technology inc. ds39026d-page 99 pic18cxx2 10.2 timer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. table 10-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper start-up of the timer1 oscillator. 10.3 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clear- ing tmr1 interrupt enable bit tmr1ie (pie1<0>). 10.4 resetting timer1 using a ccp trigger output if the ccp module is configured in compare mode to generate a ?special event trigger? (ccp1m3:ccp1m0 = 1011), this signal will reset timer1 and start an a/d conversion (if the a/d module is enabled). timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from ccp1, the write will take prece- dence. in this mode of operation, the ccpr1h:ccpr1l regis- ters pair effectively becomes the period register for timer1. 10.5 timer1 16-bit read/write mode timer1 can be configured for 16-bit reads and writes (see figure 10-2). when the rd16 control bit (t1con<7>) is set, the address for tmr1h is mapped to a buffer register for the high byte of timer1. a read from tmr1l will load the contents of the high byte of timer1 into the timer1 high byte buffer. this provides the user with the ability to accurately read all 16-bits of timer1, without having to determine whether a read of the high byte, followed by a read of the low byte, is valid, due to a rollover between reads. a write to the high byte of timer1 must also take place through the tmr1h buffer register. timer1 high byte is updated with the contents of tmr1h when a write occurs to tmr1l. this allows a user to write all 16 bits to both the high and low bytes of timer1 at once. tmr1h is updated from the high byte when tmr1l is read. the high byte of timer1 is not directly readable or writ- able in this mode. all reads and writes must take place through the timer1 high byte buffer register. writes to tmr1h do not clear the timer1 prescaler. the pres- caler is only cleared on writes to tmr1l. table 10-1: capacitor selection for the alternate oscillator osc type freq. c1 c2 lp 32 khz tbd (1) tbd (1) crystal to be tested: 32.768 khz epson c-001r32.768k-a ? 20 ppm note 1: microchip suggests 33 pf as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: capacitor values are for design guidance only. note: the special event triggers from the ccp1 module will not set interrupt flag bit tmr1if (pir1<0>).
pic18cxx2 ds39026d-page 100 ? 1999-2013 microchip technology inc. table 10-2: registers associated with timer1 as a timer/counter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the timer1 module. note 1: the pspif, pspie and pspip bits are reserved on the pic18c2x2 devices. always maintain these bits clear.
? 1999-2013 microchip technology inc. ds39026d-page 101 pic18cxx2 11.0 timer2 module the timer2 module timer has the following features: ? 8-bit timer (tmr2 register) ? 8-bit period register (pr2) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4, 1:16) ? software programmable postscaler (1:1 to 1:16) ? interrupt on tmr2 match of pr2 ? ssp module optional use of tmr2 output to gen- erate clock shift timer2 has a control register shown in register 11-1. timer2 can be shut-off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. figure 11-1 is a simplified block diagram of the timer2 module. register 11-1 shows the timer2 control regis- ter. the prescaler and postscaler selection of timer2 are controlled by this register. 11.1 timer2 operation timer2 can be used as the pwm time-base for the pwm mode of the ccp module. the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4, or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the match out- put of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, (pir1<1>)). the prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (power-on reset, mclr reset, watchdog timer reset, or brown-out reset) tmr2 is not cleared when t2con is written. register 11-1: t2con: timer2 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as '0' bit 6-3 toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale ? ? ? 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18cxx2 ds39026d-page 102 ? 1999-2013 microchip technology inc. 11.2 timer2 interrupt the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. 11.3 output of tmr2 the output of tmr2 (before the postscaler) is fed to the synchronous serial port module, which optionally uses it to generate the shift clock. figure 11-1: timer2 block diagram table 11-1: registers associated with timer2 as a timer/counter comparator tmr2 sets flag tmr2 output (1) reset postscaler prescaler pr2 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to toutps3:toutps0 t2ckps1:t2ckps0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 tmr2 timer2 module register 0000 0000 0000 0000 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the timer2 module. note 1: the pspif, pspie and pspip bits are reserved on the pic18c2x2 devices. always maintain these bits clear.
? 1999-2013 microchip technology inc. ds39026d-page 103 pic18cxx2 12.0 timer3 module the timer3 module timer/counter has the following features: ? 16-bit timer/counter (two 8-bit registers: tmr3h and tmr3l) ? readable and writable (both registers) ? internal or external clock select ? interrupt-on-overflow from ffffh to 0000h ? reset from ccp module trigger figure 12-1 is a simplified block diagram of the timer3 module. register 12-1 shows the timer3 control register. this register controls the operating mode of the timer3 module and sets the ccp clock source. register 10-1 shows the timer1 control register. this register controls the operating mode of the timer1 module, as well as contains the timer1 oscillator enable bit (t1oscen), which can be a clock source for timer3. register 12-1: t3con: time r3 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable 1 = enables register read/write of timer3 in one 16-bit operation 0 = enables register read/write of timer3 in two 8-bit operations bit 6-3 t3ccp2:t3ccp1: timer3 and timer1 to ccpx enable bits 1x = timer3 is the clock source for compare/capture ccp modules 01 = timer3 is the clock source for compare/capture of ccp2, timer1 is the clock source for compare/capture of ccp1 00 = timer1 is the clock source for compare/capture ccp modules bit 5-4 t3ckps1:t3ckps0 : timer3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 t3sync : timer3 external clock input synchronization control bit (not usable if the system clock comes from timer1/timer3.) when tmr3cs = 1: 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr3cs = 0: this bit is ignored. timer3 uses the internal clock when tmr3cs = 0. bit 1 tmr3cs: timer3 clock source select bit 1 = external clock input from timer1 oscillator or t1cki (on the rising edge after the first falling edge) 0 = internal clock (f osc /4) bit 0 tmr3on: timer3 on bit 1 = enables timer3 0 = stops timer3 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18cxx2 ds39026d-page 104 ? 1999-2013 microchip technology inc. 12.1 timer3 operation timer3 can operate in one of these modes: ?as a timer ? as a synchronous counter ? as an asynchronous counter the operating mode is determined by the clock select bit, tmr3cs (t3con<1>). when tmr3cs = 0, timer3 increments every instruc- tion cycle. when tmr3cs = 1, timer3 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. timer3 also has an internal ?reset input?. this reset can be generated by the ccp module (section 12.0). figure 12-1: timer3 block diagram figure 12-2: timer3 block diagram co nfigured in 16-bit read/write mode tmr3h tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen enable oscillator (1) tmr3if overflow interrupt f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi flag bit (3) note 1: when enable bit t1oscen is cleared, the inverter and feedback re sistor are turned off. this eliminates power drain. t13cki clr ccp special trigger t3ccpx timer3 tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen enable oscillator (1) f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi tmr3 t13cki clr ccp special trigger t3ccpx to timer1 clock input note 1: when enable bit t1oscen is cleared, the inverter and feedback re sistor are turned off. th is eliminates power drain. high byte data bus<7:0> 8 tmr3h 8 8 8 read tmr3l write tmr3l set tmr3if flag bit on overflow
? 1999-2013 microchip technology inc. ds39026d-page 105 pic18cxx2 12.2 timer1 oscillator the timer1 oscillator may be used as the clock source for timer3. the timer1 oscillator is enabled by setting the t1oscen (t1con<3>) bit. the oscillator is a low power oscillator rated up to 200 khz. see section 10.0 for further details. 12.3 timer3 interrupt the tmr3 register pair (tmr3h:tmr3l) increments from 0000h to ffffh and rolls over to 0000h. the tmr3 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit tmr3if (pir2<1>). this interrupt can be enabled/disabled by setting/clear- ing tmr3 interrupt enable bit, tmr3ie (pie2<1>). 12.4 resetting timer3 using a ccp trigger output if the ccp module is configured in compare mode to generate a ?special event trigger? (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer3. timer3 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer3 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer3 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l registers pair effectively becomes the period register for timer3. table 12-1: registers associated with timer3 as a timer/counter note: the special event triggers from the ccp module will not set interrupt flag bit tmr3if (pir1<0>). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir2 ? ? ? ? bclif lvdif tmr3if ccp2if 0000 0000 0000 0000 pie2 ? ? ? ? bclie lvdie tmr3ie ccp2ie 0000 0000 0000 0000 ipr2 ? ? ? ? bclip lvdip tmr3ip ccp2ip 0000 0000 0000 0000 tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on -000 0000 -uuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the timer1 module.
pic18cxx2 ds39026d-page 106 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 107 pic18cxx2 13.0 capture/compare/pwm (ccp) modules each ccp (capture/compare/pwm) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register, or as a pwm master/slave duty cycle register. table 13-1 shows the timer resources of the ccp module modes. the operation of ccp1 is identical to that of ccp2, with the exception of the special event trigger. therefore, operation of a ccp module in the following sections is described with respect to ccp1. table 13-2 shows the interaction of the ccp modules. register 13-1: ccp1con register/ccp2con register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5-4 dcxb1:dcxb0 : pwm duty cycle bit1 and bit0 capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs (bit1 and bit0) of the 10-bit pwm duty cycle. the upper eight bits (dcx9:dcx2) of the duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm off (resets ccpx module) 0001 = reserved 0010 = compare mode, toggle output on match (ccpxif bit is set) 0011 = reserved 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, initialize ccp pin low, on compare match force ccp pin high (ccpif bit is set) 1001 = compare mode, initialize ccp pin high, on compare match force ccp pin low (ccpif bit is set) 1010 = compare mode, generate software interrupt on compare match (ccpif bit is set, ccp pin is unaffected) 1011 = compare mode, trigger special event (ccpif bit is set) 11xx =pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18cxx2 ds39026d-page 108 ? 1999-2013 microchip technology inc. 13.1 ccp1 module capture/compare/pwm register 1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. all are readable and writable. table 13-1: ccp mode - timer resource 13.2 ccp2 module capture/compare/pwm register2 (ccpr2) is com- prised of two 8-bit registers: ccpr2l (low byte) and ccpr2h (high byte). the ccp2con register controls the operation of ccp2. all are readable and writable. table 13-2: interaction of two ccp modules ccp mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 ccpx mode ccpy mode interaction capture capture tmr1 or tmr3 time-base. time-base can be different for each ccp. capture compare the compare could be configured for the special event trigger, which clears either tmr1, or tmr3, depending upon which time-base is used. compare compare the compare(s) could be configured for the special event trigger, which clears tmr1, or tmr3, depending upon which time-base is used. pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). pwm capture none. pwm compare none.
? 1999-2013 microchip technology inc. ds39026d-page 109 pic18cxx2 13.3 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 or tmr3 registers when an event occurs on pin rc2/ccp1. an event is defined as: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ccp1if (pir1<2>) is set. it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value will be lost. 13.3.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be config- ured as an input by setting the trisc<2> bit. 13.3.2 timer1/timer3 mode selection the timers that are to be used with the capture feature (either timer1 and/or timer3) must be running in timer mode or synchronized counter mode. in asynchro- nous counter mode, the capture operation may not work. the timer to be used with each ccp module is selected in the t3con register. 13.3.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit, ccp1if, following any such change in operating mode. 13.3.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 13-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 13-1: changing between capture prescalers figure 13-1: capture mode operat ion block diagram note: if the rc2/ccp1 is configured as an out- put, a write to the port can cause a capture condition. clrf ccp1con, f ; turn ccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode ; value and ccp on movwf ccp1con ; load ccp1con with ; this value ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if tmr3 enable q?s ccp1con<3:0> ccp1 pin prescaler ? 1, 4, 16 and edge detect tmr3h tmr3l tmr1 enable t3ccp2 t3ccp2 ccpr2h ccpr2l tmr1h tmr1l set flag bit ccp2if tmr3 enable q?s ccp2con<3:0> ccp2 pin prescaler ? 1, 4, 16 and edge detect tmr3h tmr3l tmr1 enable t3ccp2 t3ccp1 t3ccp2 t3ccp1
pic18cxx2 ds39026d-page 110 ? 1999-2013 microchip technology inc. 13.4 compare mode in compare mode, the 16-bit ccpr1 (ccpr2) register value is constantly compared against either the tmr1 register pair value or the tmr3 register pair value. when a match occurs, the rc2/ccp1 (rc1/ccp2) pin is: ? driven high ? driven low ? toggle output (high to low or low to high) ? remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp2m3:ccp2m0). at the same time, interrupt flag bit, ccp1if (ccp2if) is set. 13.4.1 ccp pin configuration the user must configure the ccpx pin as an output by clearing the appropriate trisc bit. 13.4.2 timer1/timer3 mode selection timer1 and/or timer3 must be running in timer mode, or synchronized counter mode, if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 13.4.3 software interrupt mode when generate software interrupt is chosen, the ccp1 pin is not affected. only a ccp interrupt is generated (if enabled). 13.4.4 special event trigger in this mode, an internal hardware trigger is generated, which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special trigger output of ccpx resets either the tmr1 or tmr3 register pair. additionally, the ccp2 special event trigger will start an a/d conversion if the a/d module is enabled. figure 13-2: compare mode operat ion block diagram note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the data latch. note: the special event trigger from the ccp2 module will not set the timer1 or timer3 interrupt flag bits. ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin special event trigger will: reset timer1or timer3, but not set timer1 or timer3 interrupt flag bit, and set bit go/done (adcon0<2>) which starts an a/d conversion (ccp2 only) tmr3h tmr3l t3ccp2 ccpr2h ccpr2l comparator 1 0 t3ccp2 t3ccp1 qs r output logic special event trigger set flag bit ccp2if match rc1/ccp2 trisc<1> ccp2con<3:0> mode select output enable pin 01
? 1999-2013 microchip technology inc. ds39026d-page 111 pic18cxx2 table 13-3: registers associated with capture, compare, timer1 and timer3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif ( 1 ) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie ( 1 ) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip ( 1 ) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 trisc portc data direction register 1111 1111 1111 1111 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 pir2 ? ? ? ? bclif lvdif tmr3if ccp2if 0000 0000 0000 0000 pie2 ? ? ? ? bclie lvdie tmr3ie ccp2ie 0000 0000 0000 0000 ipr2 ? ? ? ? bclip lvdip tmr3ip ccp2ip 0000 0000 0000 0000 tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on -000 0000 -uuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by capture and timer1. note 1: the pspif, pspie and pspip bits are reserved on the pic18c2x2 devices. always maintain these bits clear.
pic18cxx2 ds39026d-page 112 ? 1999-2013 microchip technology inc. 13.5 pwm mode in pulse width modulation (pwm) mode, the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 13-3 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 13.5.3. figure 13-3: simplified pwm block diagram a pwm output (figure 13-4) has a time-base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 13-4: pwm output 13.5.1 pwm period the pwm period is specified by writing to the pr2 reg- ister. the pwm period can be calculated using the fol- lowing formula: pwm period = (pr2) + 1] ? 4 ? t osc ? (tmr2 prescale value) pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) ? the pwm duty cycle is latched from ccpr1l into ccpr1h 13.5.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) ? t osc ? (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2 con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the equation: note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time-base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 11.0) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a dif- ferent frequency than the pwm output. note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. f osc f pwm --------------- ?? ?? log 2 ?? log ----------------------------- b i t s = pwm resolution (max)
? 1999-2013 microchip technology inc. ds39026d-page 113 pic18cxx2 13.5.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 13-4: example pwm frequencies and resolutions at 40 mhz table 13-5: registers associated with pwm and timer2 pwm frequency 2.44 khz 9.77 khz 39.06 khz 156.25 khz 312.50 khz 416.67 khz timer prescaler (1, 4, 16)1641111 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 14 12 10 8 7 6.58 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif ( 1 ) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie ( 1 ) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip ( 1 ) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 trisc portc data direction register 1111 1111 1111 1111 tmr2 timer2 module register 0000 0000 0000 0000 pr2 timer2 module period register 1111 1111 1111 1111 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by pwm and timer2. note 1: the pspif, pspie and pspip bits are reserved on the pic18c2x2 devices. always maintain these bits clear.
pic18cxx2 ds39026d-page 114 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 115 pic18cxx2 14.0 master synchronous serial port (mssp) module 14.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the mssp module can operate in one of two modes: ? serial peripheral interface (spi tm ) ? inter-integrated circuit (i 2 c tm ) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: ?master mode ? multi-master mode ? slave mode
pic18cxx2 ds39026d-page 116 ? 1999-2013 microchip technology inc. 14.2 control registers the mssp module has three associated registers. these include a status register (sspstat) and two control registers (sspcon1 and sspcon2). register 14-1: sspstat: mssp status register r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode in i 2 c master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high speed mode (400 khz) bit 6 cke: spi clock edge select bit ckp = 0: 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck ckp = 1: 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared.) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1999-2013 microchip technology inc. ds39026d-page 117 pic18cxx2 bit 3 s: start bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared.) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c slave mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress or-ing this bit with sen, rsen, pen, rcen, or acken will indicate if the mssp is in idle mode. bit 1 ua: update address bit (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit ( i 2 c mode only): 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty register 14-1: sspstat: mssp status register (continued) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18cxx2 ds39026d-page 118 ? 1999-2013 microchip technology inc. register 14-2: sspcon1: ms sp control register1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit master mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision slave mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit in spi mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. in slave mode, the user must read the sspbuf, even if only transmitting data to avoid setting overflow. in master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by writing to the sspbuf register (must be cleared in software). 0 = no overflow in i 2 c mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a ?don?t care? in transmit mode (must be cleared in software). 0 = no overflow bit 5 sspen: synchronous serial port enable bit in both modes when enabled, these pins must be properly configured as input or output. in spi mode: 1 = enables serial port and configures sck, sdo, sdi, and ss as the source of the serial port pins 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configures the sda and scl pins as the source of the serial port pins 0 = disables serial port and configures these pins as i/o port pins legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1999-2013 microchip technology inc. ds39026d-page 119 pic18cxx2 bit 4 ckp: clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c slave mode: sck release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) in i 2 c master mode: unused in this mode bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin. 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc / (4 * (sspadd+1)) 1001 = reserved 1010 = reserved 1011 = i 2 c firmware controlled master mode (slave idle) 1100 = reserved 1101 = reserved 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled register 14-2: sspcon1: mssp co ntrol register1 (continued) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18cxx2 ds39026d-page 120 ? 1999-2013 microchip technology inc. register 14-3: sspcon2: mssp control register2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 bit 7 gcen: general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (in i 2 c master mode only) in master transmit mode: 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (in i 2 c master mode only) in master receive mode: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (in i 2 c master mode only) in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (in i 2 c master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (in i 2 c master mode only) sck release control : 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enabled bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enabled bit (in i 2 c master mode only) 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle note: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1999-2013 microchip technology inc. ds39026d-page 121 pic18cxx2 14.3 spi mode the spi mode allows 8-bits of data to be synchronously transmitted and received simultaneously. all four modes of spi are supported. to accomplish communi- cation, typically three pins are used: ? serial data out (sdo) - rc5/sdo ? serial data in (sdi) - rc4/sdi/sda ? serial clock (sck) - rc3/sck/scl/lvoin additionally, a fourth pin may be used when in a slave mode of operation: ? slave select (ss ) - ra5/ss /an4 14.3.1 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon1<5:0>) and sspstat<7:6>. these control bits allow the following to be specified: ? master mode (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? data input sample phase (middle or end of data output time) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master mode only) ? slave select mode (slave mode only) figure 14-1 shows the block diagram of the mssp module, when in spi mode. figure 14-1: mssp block diagram (spi mode) the mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr, until the received data is ready. once the 8-bits of data have been received, that byte is moved to the sspbuf register. then the buffer full detect bit, bf (sspstat<0>), and the interrupt flag bit, sspif, are set. this double buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored, and the write collision detect bit, wcol (sspcon1<7>), will be set. user software must clear the wcol bit so that it can be determined if the follow- ing write(s) to the sspbuf register completed successfully. read write internal data bus sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr tris bit 2 smp:cke sdi sdo ss sck ( )
pic18cxx2 ds39026d-page 122 ? 1999-2013 microchip technology inc. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit, bf (sspstat<0>), indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally the mssp interrupt is used to determine when the transmission/reception has com- pleted. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 14-1 shows the loading of the sspbuf (sspsr) for data transmission. example 14-1: loading the sspbuf (sspsr) register the sspsr is not directly readable or writable, and can only be accessed by addressing the sspbuf reg- ister. additionally, the mssp status register (sspstat) indicates the various status conditions. 14.3.2 enabling spi i/o to enable the serial port, ssp enable bit, sspen (sspcon1<5>), must be set. to reset or reconfigure spi mode, clear the sspen bit, re-initialize the sspcon registers, and then set the sspen bit. this configures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port func- tion, some must have their data direction bits (in the tris register) appropriately programmed. that is: ? sdi is automatically controlled by the spi module ? sdo must have trisc<5> bit cleared ? sck (master mode) must have trisc<3> bit cleared ? sck (slave mode) must have trisc<3> bit set ?ss must have trisc<4> bit set any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (tris) register to the opposite value. loop btfss sspstat, bf ;has data been received(transmit complete)? goto loop ;no movf sspbuf, w ;wreg reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit
? 1999-2013 microchip technology inc. ds39026d-page 123 pic18cxx2 14.3.3 typical connection figure 14-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their pro- grammed clock edge, and latched on the opposite edge of the clock. both processors should be pro- grammed to same clock polarity (ckp), then both con- trollers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: ? master sends data ? ? ? slave sends dummy data ? master sends data ? ? ? slave sends data ? master sends dummy data ? ? ? slave sends data figure 14-2: spi master/s lave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm3:sspm0 = 00xxb serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm3:sspm0 = 010xb serial clock
pic18cxx2 ds39026d-page 124 ? 1999-2013 microchip technology inc. 14.3.4 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 14-2) is to broad- cast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be dis- abled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?line activity monitor? mode. the clock polarity is selected by appropriately program- ming the ckp bit (sspcon1<4>). this then, would give waveforms for spi communication as shown in figure 14-3, figure 14-5, and figure 14-6, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: ?f osc /4 (or t cy ) ?f osc /16 (or 4 ? t cy ) ?f osc /64 (or 16 ? t cy ) ? timer2 output/2 this allows a maximum data rate (at 40 mhz) of 10.00 mbps. figure 14-3 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 14-3: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit0 sdi sspif (smp = 1) (smp = 0) (smp = 1) cke = 1) cke = 0) cke = 1) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (cke = 0) (cke = 1) next q4 cycle after q2 ?
? 1999-2013 microchip technology inc. ds39026d-page 125 pic18cxx2 14.3.5 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. 14.3.6 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 04h). the pin must not be driven low for the ss pin to function as an input. the data latch must be high. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the mid- dle of a transmitted byte, and becomes a floating output. external pull-up/pull-down resistors may be desirable, depending on the application. when the spi module resets, the bit counter is forced to 0. this can be done by either forcing the ss pin to a high level, or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver, the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function), since it cannot create a bus conflict. figure 14-4: slave synchroniza tion waveform note 1: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke set, then the ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 sdo bit7 bit6 bit7 sspif interrupt (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss flag bit0 bit7 bit0 next q4 cycle after q2 ?
pic18cxx2 ds39026d-page 126 ? 1999-2013 microchip technology inc. figure 14-5: spi mode waveform (slave mode with cke = 0) figure 14-6: spi mode waveform (slave mode with cke = 1) sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif interrupt (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss flag optional next q4 cycle after q2 ? sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif interrupt (smp = 0) cke = 1) cke = 1) (smp = 0) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2 ?
? 1999-2013 microchip technology inc. ds39026d-page 127 pic18cxx2 14.3.7 sleep operation in master mode, all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from sleep. after the device returns to normal mode, the module will continue to transmit/ receive data. in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode, and data to be shifted into the spi transmit/receive shift register. when all 8-bits have been received, the mssp inter- rupt flag bit will be set and if enabled, will wake the device from sleep. 14.3.8 effects of a reset a reset disables the mssp module and terminates the current transfer. 14.3.9 bus mode compatibility table 14-1 shows the compatibility between the stan- dard spi modes and the states of the ckp and cke control bits. table 14-1: spi bus modes there is also a smp bit which controls when the data is sampled. table 14-2: registers associat ed with spi operation standard spi mode terminology control bits state ckp cke 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif ( 1 ) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie ( 1 ) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip ( 1 ) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 trisc portc data direction register 1111 1111 1111 1111 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 trisa ? porta data direction register --11 1111 --11 1111 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the mssp in spi mode. note 1: the pspif, pspie and pspip bits are reserved on the pi c18c2x2 devices. always ma intain these bits clear.
pic18cxx2 ds39026d-page 128 ? 1999-2013 microchip technology inc. 14.4 mssp i 2 c operation the mssp module in i 2 c mode, fully implements all master and slave functions (including general call sup- port) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master func- tion). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer. these are the rc3/ sck/scl pin, which is the clock (scl), and the rc4/ sdi/sda pin, which is the data (sda). the user must configure these pins as inputs or outputs through the trisc<4:3> bits. the mssp module functions are enabled by setting mssp enable bit sspen (sspcon<5>). figure 14-7: mssp block diagram (i 2 c mode) the mssp module has six registers for i 2 c operation. these are the: ? mssp control register1 (sspcon1) ? mssp control register2 (sspcon2) ? mssp status register (sspstat) ? serial receive/transmit buffer (sspbuf) ? mssp shift register (sspsr) - not directly accessible ? mssp address register (sspadd) the sspcon1 register allows control of the i 2 c oper- ation. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ?i 2 c master mode, clock = osc/4 (sspadd +1) ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ?i 2 c slave mode (7-bit address), with start and stop bit interrupts enabled ?i 2 c slave mode (10-bit address), with start and stop bit interrupts enabled ?i 2 c firmware controlled master operation, slave is idle selection of any i 2 c mode with the sspen bit set, forces the scl and sda pins to be open drain, pro- vided these pins are programmed to be inputs by set- ting the appropriate trisc bits. 14.4.1 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the mssp module will override the input state with the output data when required (slave-transmitter). when an address is matched or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse and load the sspbuf register with the received value cur- rently in the sspsr register. there are certain conditions that will cause the mssp module not to give this ack pulse. these are if either (or both): a) the buffer full bit bf (sspstat<0>) was set before the transfer was received. b) the overflow bit sspov (sspcon<6>) was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. the bf bit is cleared by reading the sspbuf register, while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, are shown in timing parameter #100 and parameter #101. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/scl rc4/ shift clock msb sdi/ lsb sda
? 1999-2013 microchip technology inc. ds39026d-page 129 pic18cxx2 14.4.1.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start con- dition, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit bf is set. c) an ack pulse is generated. d) mssp interrupt flag bit sspif (pir1<3>) is set (interrupt is generated if enabled) on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ? 1111 0 a9 a8 0 ?, where a9 and a8 are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7-9 for slave-transmitter: 1. receive first (high) byte of address (bits sspif, bf and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the first (high) byte of address. if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. 14.4.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte overflow condition exists, then no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit bf (sspstat<0>) is set, or bit sspov (sspcon<6>) is set. an mssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware. the sspstat register is used to determine the status of the byte. 14.4.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and pin rc3/sck/scl is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr regis- ter. then pin rc3/sck/scl should be enabled by set- ting bit ckp (sspcon<4>). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretch- ing the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 14-9). an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared in software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line is high (not ack ), then the data transfer is complete. when the ack is latched by the slave, the slave logic is reset (resets sspstat register) and the slave monitors for another occurrence of the start bit. if the sda line was low (ack ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr regis- ter. pin rc3/sck/scl should be enabled by setting bit ckp.
pic18cxx2 ds39026d-page 130 ? 1999-2013 microchip technology inc. figure 14-8: i 2 c slave mode waveforms for reception (7-bit address) figure 14-9: i 2 c slave mode waveforms for transmission (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 123456 789 1234 56 7 89 1234 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w =0 receiving address sspif bf (sspstat<0>) sspov (sspcon1<6>) not ack ack is not sent. sda scl sspif bf (sspstat<0>) ckp (sspcon1<4>) a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 not ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written to before the ckp bit can be set) r/w = 0
? 1999-2013 microchip technology inc. ds39026d-page 131 pic18cxx2 figure 14-10: i 2 c slave mode waveform (transmission 10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 1 1 1 1 0 a8 r/w =1 ack ack r/w = 0 ack receive first byte of address cleared in software master sends nack a9 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated. ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf flag sr cleared in software write of sspbuf initiates transmit cleared in software transmit is complete ckp has to be set for clock to be released bus master terminates transfer
pic18cxx2 ds39026d-page 132 ? 1999-2013 microchip technology inc. figure 14-11: i 2 c slave mode waveform (reception 10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6 a5 a4 a3 a2a1 a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer d2 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated with ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack r/w = 1 cleared in software dummy read of sspbuf to clear bf flag read of sspbuf clears bf flag cleared by hardware when sspadd is updated with low byte of address. high byte of address.
? 1999-2013 microchip technology inc. ds39026d-page 133 pic18cxx2 14.4.2 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowl- edge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all 0?s with r/w = 0. the general call address is recognized when the gen- eral call enable bit (gcen) is enabled (sspcon2<7> is set). following a start bit detect, 8-bits are shifted into the sspsr and the address is compared against the sspadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf flag bit is set (eighth bit), and on the falling edge of the ninth bit (ack bit), the sspif interrupt flag bit is set. when the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the sspbuf. the value can be used to determine if the address was device specific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match, and the ua bit is set (sspstat<1>). if the general call address is sampled when the gcen bit is set, while the slave is configured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set, and the slave will begin receiving data after the acknowledge (figure 14-12). figure 14-12: slave mode general call address sequence (7 or 10-bit address mode) 14.4.3 master mode master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle, with both the s and p bits clear. in master mode, the scl and sda lines are manipu- lated by the mssp hardware. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt, if enabled): ? start condition ? stop condition ? data transfer byte transmitted/received ? acknowledge transmit ? repeated start sda scl s sspif bf (sspstat<0>) sspov (sspcon1<6>) cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen (sspcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack, set interrupt '0' '1'
pic18cxx2 ds39026d-page 134 ? 1999-2013 microchip technology inc. 14.4.4 i 2 c master mode support master mode is enabled by setting and clearing the appropriate sspm bits in sspcon1 and by setting the sspen bit. once master mode is enabled, the user has six options. 1. assert a start condition on sda and scl. 2. assert a repeated start condition on sda and scl. 3. write to the sspbuf register initiating transmis- sion of data/address. 4. generate a stop condition on sda and scl. 5. configure the i 2 c port to receive data. 6. generate an acknowledge condition at the end of a received byte of data. figure 14-13: mssp block diagram (i 2 c master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to imitate transmission, before the start condition is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur. read write sspsr start bit, stop bit, start bit detect sspbuf internal data bus set/reset, s, p, wcol (sspstat) shift clock msb lsb sda acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset ackstat, pen (sspcon2) rate generator sspm3:sspm0
? 1999-2013 microchip technology inc. ds39026d-page 135 pic18cxx2 14.4.4.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a trans- fer is ended with a stop condition or with a repeated start condition. since the repeated start condi- tion is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic '0'. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic '1'. thus, the first byte transmitted is a 7-bit slave address followed by a '1' to indicate receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for the spi mode opera- tion is now used to set the scl clock frequency for either 100 khz, 400 khz, or 1 mhz i 2 c operation. the baud rate generator reload value is contained in the lower 7 bits of the sspadd register. the baud rate generator will automatically begin counting on a write to the sspbuf. once the given operation is complete, (i.e., transmission of the last data bit is followed by ack), the internal clock will automatically stop counting and the scl pin will remain in its last state. a typical transmit sequence would go as follows: a) the user generates a start condition by set- ting the start enable bit, sen (sspcon2<0>). b) sspif is set. the mssp module will wait the required start time before any other operation takes place. c) the user loads the sspbuf with the address to transmit. d) address is shifted out the sda pin until all 8 bits are transmitted. e) the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). f) the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. g) the user loads the sspbuf with eight bits of data. h) data is shifted out the sda pin until all 8 bits are transmitted. i) the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). j) the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. k) the user generates a stop condition by setting the stop enable bit, pen (sspcon2<2>). l) interrupt is generated once the stop condition is complete.
pic18cxx2 ds39026d-page 136 ? 1999-2013 microchip technology inc. 14.4.5 baud rate generator in i 2 c master mode, the reload value for the brg is located in the lower 7 bits of the sspadd register (figure 14-14). when the brg is loaded with this value, the brg counts down to 0 and stops until another reload has taken place. the brg count is dec- remented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. if clock arbitration is taking place, for instance, the brg will be reloaded when the scl pin is sampled high (figure 14-15). figure 14-14: baud rate generato r block diagram figure 14-15: baud rate generator timing with clock arbitration sspm3:sspm0 brg down counter clkout f osc /4 sspadd<6:0> sspm3:sspm0 scl reload control reload sda scl scl de-asserted but slave holds dx-1 dx brg scl is sampled high, reload takes place and brg starts its count. 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles
? 1999-2013 microchip technology inc. ds39026d-page 137 pic18cxx2 14.4.6 i 2 c master mode start condition timing to initiate a start condition, the user sets the start condition enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate genera- tor is reloaded with the contents of sspadd<6:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low, while scl is high, is the start condition and causes the s bit (sspstat<3>) to be set. follow- ing this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2<0>) will be automatically cleared by hardware, the baud rate generator is suspended leaving the sda line held low and the start condition is complete. 14.4.6.1 wcol status flag if the user writes the sspbuf when a start sequence is in progress, the wcol is set and the con- tents of the buffer are unchanged (the write doesn?t occur). figure 14-16: first start bit timing note: if, at the beginning of the start condition, the sda and scl pins are already sam- pled low, or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag, bclif is set, the start condition is aborted, and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1, at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here. set s bit (sspstat<3>) and sets sspif bit
pic18cxx2 ds39026d-page 138 ? 1999-2013 microchip technology inc. 14.4.7 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded with the contents of sspadd<5:0> and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be de-asserted (brought high). when scl is sampled high, the baud rate generator is reloaded with the con- tents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0) for one t brg , while scl is high. following this, the rsen bit (sspcon2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode), or eight bits of data (7-bit mode). 14.4.7.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 14-17: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low to high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data "1". note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here. falling edge of ninth clock end of xmit at completion of start bit, hardware clear rsen bit 1st bit set s (sspstat<3>) t brg t brg sda = 1, sda = 1, scl (no change) scl = 1 occurs here. t brg t brg t brg and set sspif
? 1999-2013 microchip technology inc. ds39026d-page 139 pic18cxx2 14.4.8 i 2 c master mode transmission transmission of a data byte, a 7-bit address, or the other half of a 10-bit address, is accomplished by sim- ply writing a value to the sspbuf register. this action will set the buffer full flag bit, bf, and allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time specification parameter 106). scl is held low for one baud rate generator roll- over count (t brg ). data should be valid before scl is released high (see data setup time specification parameter 107). when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. allowing the slave device being addressed to respond with an ack bit during the ninth bit time, if an address match occurs, or if data was received properly. the sta- tus of ack is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate gener- ator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged (figure 14-18). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the fall- ing edge of the eighth clock, the master will de-assert the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2<6>). following the falling edge of the ninth clock transmis- sion of the address, the sspif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 14.4.8.1 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared, when all 8 bits are shifted out. 14.4.8.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress, (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). wcol must be cleared in software. 14.4.8.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0), and is set when the slave does not acknowl- edge (ack = 1). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 14.4.9 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting, and on each rollover, the state of the scl pin changes (high to low/ low to high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate genera- tor is suspended from counting, holding scl low. the mssp is now in idle state, awaiting the next com- mand. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception, by setting the acknowledge sequence enable bit, acken (sspcon2<4>). 14.4.9.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 14.4.9.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspsr and the bf flag bit is already set from a previous reception. 14.4.9.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). note: the mssp module must be in an idle state before the rcen bit is set, or the rcen bit will be disregarded.
pic18cxx2 ds39026d-page 140 ? 1999-2013 microchip technology inc. figure 14-18: i 2 c master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7d6d5d4d3d2d1d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition sen cleared by hardware. s sspbuf written with 7 bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared in software sspbuf written pen cleared in software r/w
? 1999-2013 microchip technology inc. ds39026d-page 141 pic18cxx2 figure 14-19: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1) write to sspbuf occurs here ack from slave master configured as a receiver by programming sspcon2<3>, (rcen = 1) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0, scl = 1 while cpu (sspstat<0>) ack last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken start acknowledge sequence sspov is set because sspbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared in software sda = ackdt = 0
pic18cxx2 ds39026d-page 142 ? 1999-2013 microchip technology inc. 14.4.10 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit is presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate gen- erator then counts for one rollover period (t brg ) and the scl pin is de-asserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate gener- ator counts for t brg . the scl pin is then pulled low. fol- lowing this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode (figure 14-20). 14.4.10.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). 14.4.11 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspcon2<2>). at the end of a receive/trans- mit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to 0. when the baud rate generator times out, the scl pin will be brought high, and one t brg (baud rate generator rollover count) later, the sda pin will be de-asserted. when the sda pin is sampled high while scl is high, the p bit (sspstat<4>) is set. a t brg later, the pen bit is cleared and the sspif bit is set (figure 14-21). 14.4.11.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the con- tents of the buffer are unchanged (the write doesn?t occur). figure 14-20: acknowledge sequen ce waveform note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg of receive ack 8 acken = 1, ackdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software
? 1999-2013 microchip technology inc. ds39026d-page 143 pic18cxx2 figure 14-21: stop cond ition receive or transmit mode 14.4.12 clock arbitration clock arbitration occurs when the master, during any receive, transmit, or repeated start/stop condi- tion, de-asserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count, in the event that the clock is held low by an external device (figure 14-22). 14.4.13 sleep operation while in sleep mode, the i 2 c module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 14.4.14 effect of a reset a reset disables the mssp module and terminates the current transfer. figure 14-22: clock arbitrat ion timing in master transmit mode scl sda sda asserted low before rising edge of clock write to sspcon2 set pen falling edge of scl = 1 for tbrg, followed by sda = 1 for tbrg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set t brg to setup stop condition . ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set scl sda brg overflow, release scl, if scl = 1, load brg with sspadd<6:0>, and start count brg overflow occurs, release scl, slave device holds scl low. scl = 1 brg starts counting clock high interval. scl line sampled once every machine cycle (t osc 2 4). hold off brg until scl is sampled high. t brg t brg t brg to measure high time interval
pic18cxx2 ds39026d-page 144 ? 1999-2013 microchip technology inc. 14.4.15 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset, or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat<4>) is set, or the bus is idle with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will gener- ate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored, for arbitration, to see if the signal level is the expected output level. this check is performed in hard- ware, with the result placed in the bclif bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition 14.4.16 multi -master communication, bus collision, and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a '1' on sda by letting sda float high and another master asserts a '0'. when the scl pin floats high, data should be stable. if the expected data on sda is a '1' and the data sampled on the sda pin = '0', then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif and reset the i 2 c port to its idle state (figure 14-23). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are de-asserted, and the sspbuf can be written to. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop, or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are de-asserted, and the respective control bits in the sspcon2 register are cleared. when the user ser- vices the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit, regardless of where the trans- mitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the determination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register, or the bus is idle and the s and p bits are cleared. figure 14-23: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high data doesn?t match what is driven bus collision has occurred. set bus collision interrupt (bclif) by the master. by master data changes while scl = 0
? 1999-2013 microchip technology inc. ds39026d-page 145 pic18cxx2 14.4.16.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition (figure 14-24). b) scl is sampled low before sda is asserted low (figure 14-25). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: ? the start condition is aborted, ? the bclif flag is set, and ? the mssp module is reset to its idle state (figure 14-24). the start condition begins with the sda and scl pins de-asserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early (figure 14-26). if, however, a '1' is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0, and during this time, if the scl pins are sampled as '0', a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 14-24: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition, is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision, because the two masters must be allowed to arbitrate the first address follow- ing the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start, or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1, scl=1 sda = 0, scl = 1. bclif s sspif sda = 0, scl = 1. sspif and bclif are cleared in software sspif and bclif are cleared in software . set bclif, set bclif. start condition.
pic18cxx2 ds39026d-page 146 ? 1999-2013 microchip technology inc. figure 14-25: bus collision during st art condition (scl = 0) figure 14-26: brg reset due to sda arbitration during start condition sda scl sen bus collision occurs, set bclif scl = 0 before sda = 0, set sen, enable start sequence if sda = 1, scl = 1 t brg t brg sda = 0, scl = 1 bclif s sspif interrupt cleared in software bus collision occurs, set bclif scl = 0 before brg time-out, '0' '0' '0' '0' sda scl sen set s set sen, enable start sequence if sda = 1, scl = 1 less than t brg t brg sda = 0, scl = 1 bclif s sspif s interrupts cleared in software set sspif sda = 0, scl = 1 sda pulled low by other master. reset brg and assert sda. scl pulled low after brg time-out set sspif '0'
? 1999-2013 microchip technology inc. ds39026d-page 147 pic18cxx2 14.4.16.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indi- cating that another master is attempting to trans- mit a data ?1?. when the user de-asserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0> and counts down to 0. the scl pin is then de-asserted, and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ?0?, figure 14-27). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high to low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high to low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ?1? during the repeated start condi- tion, figure 14-28. if, at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 14-27: bus collision during a repeat ed start condition (case 1) figure 14-28: bus collision during repeat ed start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0, set bclif and release sda and scl. cleared in software '0' '0' sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl. t brg t brg '0'
pic18cxx2 ds39026d-page 148 ? 1999-2013 microchip technology inc. 14.4.16.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been de-asserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is de-asserted, scl is sam- pled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data '0' (figure 14-29). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempt- ing to drive a data '0' (figure 14-30). figure 14-29: bus collision during a stop condition (case 1) figure 14-30: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif '0' '0' sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high set bclif '0' '0'
? 1999-2013 microchip technology inc. ds39026d-page 149 pic18cxx2 15.0 addressable universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial com- munications interface or sci.) the usart can be con- figured as a full duplex asynchronous system that can communicate with peripheral devices, such as crt ter- minals and personal computers, or it can be configured as a half-duplex synchronous system that can commu- nicate with peripheral devices, such as a/d or d/a inte- grated circuits, serial eeproms, etc. the usart can be configured in the following modes: ? asynchronous (full duplex) ? synchronous - master (half duplex) ? synchronous - slave (half duplex) in order to configure pins rc6/tx/ck and rc7/rx/dt as the universal synchronous asynchronous receiver transmitter: ? bit spen (rcsta<7>) must be set (= 1), and ? bits trisc<7:6> must be cleared (= 0). register 15-1 shows the transmit status and control register (txsta) and register 15-2 shows the receive status and control register (rcsta). register 15-1: txsta: transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync ?brghtrmttx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don?t care synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4 sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as '0' bit 2 brgh : high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode bit 1 trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data. can be address/data bit or a parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18cxx2 ds39026d-page 150 ? 1999-2013 microchip technology inc. register 15-2: rcsta: receive status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled bit 6 rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren : single receive enable bit asynchronous mode : don?t care synchronous mode - master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode - slave: unused in this mode bit 4 cren : continuous receive enable bit asynchronous mode: 1 = enables continuous receive 0 = disables continuous receive synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden : address detect enable bit asynchronous mode 9-bit (rx9 = 1): 1 = enables address detection, enable interrupt and load of the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received, and ninth bit can be used as parity bit bit 2 ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data, can be address/data bit or a parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 1999-2013 microchip technology inc. ds39026d-page 151 pic18cxx2 15.1 usart baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode, bit brgh (txsta<2>) also controls the baud rate. in synchronous mode, bit brgh is ignored. table 15-1 shows the formula for computation of the baud rate for different usart modes, which only apply in master mode (internal clock). given the desired baud rate and f osc , the nearest integer value for the spbrg register can be calculated using the formula in table 15-1. from this, the error in baud rate can be determined. example 15-1 shows the calculation of the baud rate error for the following conditions: ?f osc = 16 mhz ? desired baud rate = 9600 ? brgh = 0 ? sync = 0 it may be advantageous to use the high baud rate (brgh = 1), even for slower baud clocks. this is because the f osc /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before output- ting the new baud rate. 15.1.1 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. example 15-1: calculat ing baud rate error table 15-1: baud rate formula table 15-2: registers associated with baud rate generator desired baud rate = f osc / (64 (x + 1)) solving for x: x = ( (f osc / desired baud rate) / 64 ) - 1 x = ((16000000 / 9600) / 64) - 1 x = [25.042] = 25 calculated baud rate = 16000000 / (64 (25 + 1)) = 9615 error = (calculated baud ra te - desired baud rate) desired baud rate = (9615 - 9600) / 9600 =0.16% sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64(x+1)) (synchronous) baud rate = f osc /(4(x+1)) baud rate = f osc /(16(x+1)) na legend: x = value in spbrg (0 to 255) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used by the brg.
pic18cxx2 ds39026d-page 152 ? 1999-2013 microchip technology inc. table 15-3: baud rates for synchronous mode baud rate (k) f osc = 40 mhz f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz actual rate (k) % error spbrg value (decimal) actua l rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3na? ?na? ?na? ?na? ? 1.2na? ?na? ?na? ?na? ? 2.4na? ?na? ?na? ?na? ? 9.6 na ? ? na ? ? na ? ? 9.766 +1.73 255 19.2 na ? ? 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 76.8 76.92 0 129 76.92 +0.16 64 76.92 +0.16 51 75.76 -1.36 32 96 96.15 0 103 96.15 +0.16 51 95.24 -0.79 41 96.15 +0.16 25 300 303.03 -0.01 32 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7 500 500.00 0 19 500 0 9 500 0 7 500 0 4 high 39.06 ? 255 5000 ? 0 4000 ? 0 2500 ? 0 low 10000.00 ? 0 19.53 ? 255 15.625 ? 255 9.766 ? 255 baud rate (k) f osc = 7.15909 mhz f osc = 5.0688 mhz f osc = 4 mhz f osc = 3.579545 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 na ? ? na ? ? na ? ?? na ? ? 1.2na? ? na? ? na? ? na? ? 2.4na? ? na? ? na? ? na? ? 9.6 9.622 +0.23 185 9.6 0 131 9.615 +0.16 103 9.622 +0.23 92 19.2 19.24 +0.23 92 19.2 0 65 19.231 +0.16 51 19.04 -0.83 46 76.8 77.82 +1.32 22 79.2 +3.13 15 76.923 +0.16 12 74.57 -2.90 11 96 94.20 -1.88 18 97.48 +1.54 12 1000 +4.17 9 99.43 +3.57 8 300 298.3 -0.57 5 316.8 +5.60 3 na ? ? 298.3 -0.57 2 500 na ? ? na ? ? na ? ? na ? ? high 1789.8 ? 0 1267 ? 0 100 ? 0 894.9 ? 0 low 6.991 ? 255 4.950 ? 255 3.906 ? 255 3.496 ? 255 baud rate (k) f osc = 1 mhz f osc = 32.768 khz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 na ? ? 0.303 +1.14 26 1.2 1.202 +0.16 207 1.170 -2.48 6 2.4 2.404 +0.16 103 na ? ? 9.6 9.615 +0.16 25 na ? ? 19.2 19.24 +0.16 12 na ? ? 76.8 83.34 +8.51 2 na ? ? 96 na ? ? na ? ? 300 na ? ? na ? ? 500 na ? ? na ? ? high 250 ? 0 8.192 ? 0 low 0.9766 ? 255 0.032 ? 255
? 1999-2013 microchip technology inc. ds39026d-page 153 pic18cxx2 table 15-4: baud rates for asynchro nous mode (brgh = 0) baud rate (k) f osc = 40 mhz f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 na ? ? na ? ? na ? ? na ? ? 1.2 na ? ? 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 2.4 2.44 -1.70 255 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64 9.6 9.62 -0.16 64 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15 19.2 18.94 +1.38 32 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7 76.8 78.13 -1.70 7 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1 96 89.29 +7.52 6 104.2 +8.51 2 na ? ? na ? ? 300 312.50 -4.00 1 312.5 +4.17 0 na ? ? na ? ? 500 625.00 -20.00 0 na ? ? na ? ? na ? ? high 2.44 ? 255 312.5 ? 0 250 ? 0 156.3 ? 0 low 625.00 ? 0 1.221 ? 255 0.977 ? 255 0.6104 ? 255 baud rate (k) f osc = 7.15909 mhz f osc = 5.0688 mhz f osc = 4 mhz f osc = 3.579545 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 na ? ? 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185 1.2 1.203 +0.23 92 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46 2.4 2.380 -0.83 46 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22 9.6 9.322 -2.90 11 9.9 +3.13 7 na ? ? 9.322 -2.90 5 19.2 18.64 -2.90 5 19.8 +3.13 3 na ? ? 18.64 -2.90 2 76.8 na ? ? 79.2 +3.13 0 na ? ? na ? ? 96 na ? ? na ? ? na ? ? na ? ? 300 na ? ? na ? ? na ? ? na ? ? 500 na ? ? na ? ? na ? ? na ? ? high 111.9 ? 0 79.2 ? 0 62.500 ? 0 55.93 ? 0 low 0.437 ? 255 0.3094 ? 255 3.906 ? 255 0.2185 ? 255 baud rate (k) f osc = 1 mhz f osc = 32.768 khz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 +0.16 51 0.256 -14.67 1 1.2 1.202 +0.16 12 na ? ? 2.4 2.232 -6.99 6 na ? ? 9.6 na ? ? na ? ? 19.2 na ? ? na ? ? 76.8 na ? ? na ? ? 96 na ? ? na ? ? 300 na ? ? na ? ? 500 na ? ? na ? ? high 15.63 ? 0 0.512 ? 0 low 0.0610 ? 255 0.0020 ? 255
pic18cxx2 ds39026d-page 154 ? 1999-2013 microchip technology inc. table 15-5: baud rates for asynchronous mode (brgh = 1) baud rate (k) f osc = 40 mhz f osc = 20 mhz f osc = 16 mhz f osc = 10 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 9.6 9.77 -1.70 255 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 19.2 19.23 -0.16 129 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 38.4 38.46 -0.16 64 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15 57.6 58.14 -0.93 42 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10 115.2 113.64 +1.38 21 113.63 -1.36 10 111.11 -3.55 8 125 +8.51 4 250 250.00 0 9 250 0 4 250 0 3 na ? ? 625 625.00 0 3 625 0 1 na ? ? 625 0 0 1250 1250.00 0 1 1250 0 0 na ? ? na ? ? baud rate (k) f osc = 7.16mhz f osc = 5.068 mhz f osc = 4 mhz f osc = 3.579545 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 9.6 9.520 -0.83 46 9.6 0 32 na ? ? 9.727 +1.32 22 19.2 19.454 +1.32 22 18.645 -2.94 16 1.202 +0.17 207 18.643 -2.90 11 38.4 37.286 -2.90 11 39.6 +3.12 7 2.403 +0.13 103 37.286 -2.90 5 57.6 55.930 -2.90 7 52.8 -8.33 5 9.615 +0.16 25 55.930 -2.90 3 115.2 111.860 -2.90 3 105.6 -8.33 2 19.231 +0.16 12 111.86 -2.90 1 250 na ? ? na ? ? na ? ? 223.72 -10.51 0 625 na ? ? na ? ? na ? ? na ? ? 1250 na ? ? na ? ? na ? ? na ? ? baud rate (k) f osc = 1 mhz f osc = 32.768 khz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 9.6 8.928 -6.99 6 na ? ? 19.2 20.833 +8.51 2 na ? ? 38.4 31.25 -18.61 1 na ? ? 57.6 62.5 +8.51 0 na ? ? 115.2 na ? ? na ? ? 250 na ? ? na ? ? 625 na ? ? na ? ? 1250 na ? ? na ? ?
? 1999-2013 microchip technology inc. ds39026d-page 155 pic18cxx2 15.2 usart asynchronous mode in this mode, the usart uses standard non-return-to- zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8-bits. an on-chip dedicated 8-bit baud rate genera- tor can be used to derive standard baud rate frequen- cies from the oscillator. the usart transmits and receives the lsb first. the usart?s transmitter and receiver are functionally independent, but use the same data format and baud rate. the baud rate gener- ator produces a clock, either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). asynchro- nous mode is stopped during sleep. asynchronous mode is selected by clearing bit sync (txsta<4>). the usart asynchronous module consists of the fol- lowing important elements: ? baud rate generator ? sampling circuit ? asynchronous transmitter ? asynchronous receiver 15.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 15-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and flag bit txif (pir1<4>) is set. this interrupt can be enabled/disabled by setting/clearing enable bit, txie ( pie1<4>). flag bit txif will be set, regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicated the sta- tus of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. sta- tus bit trmt is a read only bit, which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. to set up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh (section 15.1). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set transmit bit tx9. can be used as address/data bit. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts trans- mission). figure 15-1: usart transmit block diagram note 1: the tsr register is not mapped in data memory, so it is not available to the user. 2: flag bit txif is set when enable bit txen is set. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8 ?????????
pic18cxx2 ds39026d-page 156 ? 1999-2013 microchip technology inc. figure 15-2: asynchronous transmission figure 15-3: asynchronous transmiss ion (back to back) table 15-6: registers associated wi th asynchronous transmission word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous transmission. note 1: the pspif, pspie and pspip bits are reserved on the pic18c2x2 devices. always maintain these bits clear.
? 1999-2013 microchip technology inc. ds39026d-page 157 pic18cxx2 15.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 15-4. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter oper- ates at the bit rate, or at f osc . this mode would typi- cally be used in rs-232 systems. to set up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh (section 15.1). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit rcie. 4. if 9-bit reception is desired, set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie was set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. 15.2.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is required, set the brgh bit. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rcip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rcif bit will be set when reception is com- plete. the interrupt will be acknowledged if the rcie and gie bits are set. 8. read the rcsta register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcreg to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 15-4: usart receive block diagram x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 ? 64 ? 16 or stop start (8) 7 1 0 rx9 ???????
pic18cxx2 ds39026d-page 158 ? 1999-2013 microchip technology inc. figure 15-5: asynchronous reception table 15-7: registers associated wi th asynchronous reception start bit bit7/8 bit1 bit0 bit7/8 bit0 stop bit start bit start bit bit7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, cau sing the oerr (overrun) bit to be set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous reception. note 1: the pspif, pspie and pspip bits are reserved on the pic18c2x2 devices. always maintain these bits clear.
? 1999-2013 microchip technology inc. ds39026d-page 159 pic18cxx2 15.3 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner, (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta<4>). in addition, enable bit spen (rcsta<7>) is set in order to configure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta<7>). 15.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 15-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one t cycle ), the txreg is empty and inter- rupt bit txif (pir1<4>) is set. the interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set, regardless of the state of enable bit txie, and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. trmt is a read only bit, which is set when the tsr is empty. no inter- rupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory, so it is not available to the user. to set up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate (section 15.1). 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. table 15-8: registers associated with synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous master transmission. note 1: the pspif, pspie and pspip bits are reserved on the pic18c2x2 devices. always maintain these bits clear.
pic18cxx2 ds39026d-page 160 ? 1999-2013 microchip technology inc. figure 15-6: synchronous t ransmission figure 15-7: synchronous transmission (through txen) bit 0 bit 1 bit 7 word 1 q1 q2 q3q4 q1 q2 q3 q4 q1 q2q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q3q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt rc6/tx/ck pin write to txreg reg txif bit (interrupt flag) trmt txen bit '1' '1' word 2 trmt bit write word 1 write word 2 note: sync master mode; spbrg = '0'. continuous transmission of two 8-bit words. pin rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit0 bit1 bit2 bit6 bit7 txen bit
? 1999-2013 microchip technology inc. ds39026d-page 161 pic18cxx2 15.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit sren (rcsta<5>), or enable bit cren (rcsta<4>). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. to set up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate (section 15.1). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set enable bit rcie. 5. if 9-bit reception is desired, set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit rcif will be set when reception is complete and an interrupt will be generated if the enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. table 15-9: registers associated with synchronous master reception figure 15-8: synchronous reception (master mode, sren) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous master reception. note 1: the pspif, pspie and pspip bits are reserved on the pic18c2x2 devices. always maintain these bits clear. cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 '0' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 '0' q1 q2 q3 q4 note: timing diagram demonstrates sync master mode with bit sren = '1' and bit brgh = '0'.
pic18cxx2 ds39026d-page 162 ? 1999-2013 microchip technology inc. 15.4 usart synchronous slave mode synchronous slave mode differs from the master mode in the fact that the shift clock is supplied externally at the rc6/tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta<7>). 15.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical, except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will now be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave transmission: 1. enable the synchronous slave serial port by set- ting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. table 15-10: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous slave transmission. note 1: the pspif, pspie and pspip bits are reserved on the pic18c2x2 devices. always maintain these bits clear.
? 1999-2013 microchip technology inc. ds39026d-page 163 pic18cxx2 15.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode and bit sren, which is a ?don't care? in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register, and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is com- plete. an interrupt will be generated if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren. table 15-11: registers associated wi th synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous slave reception. note 1: the pspif, pspie and pspip bits are reserved on the pic18c2x2 devices. always maintain these bits clear.
pic18cxx2 ds39026d-page 164 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 165 pic18cxx2 16.0 compatible 10-bit analog- to-digital converter (a/d) module the analog-to-digital (a/d) converter module has five inputs for the pic18c2x2 devices and eight for the pic18c4x2 devices. this module has the adcon0 and adcon1 register definitions that are compatible with the mid-range a/d module. the a/d allows conversion of an analog input signal to a corresponding 10-bit digital number. the a/d module has four registers. these registers are: ? a/d result high register (adresh) ? a/d result low register (adresl) ? a/d control register 0 (adcon0) ? a/d control register 1 (adcon1) the adcon0 register, shown in register 16-1, con- trols the operation of the a/d module. the adcon1 register, shown in register 16-2, configures the func- tions of the port pins. register 16-1: adcon0 register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done ?adon bit 7 bit 0 bit 7-6 adcs1:adcs0: a/d conversion clock select bits (adcon0 bits in bold ) bit 5-3 chs2:chs0: analog channel select bits 000 = channel 0 (an0) 001 = channel 1 (an1) 010 = channel 2 (an2) 011 = channel 3 (an3) 100 = channel 4 (an4) 101 = channel 5 (an5) 110 = channel 6 (an6) 111 = channel 7 (an7) note: the pic18c2x2 devices do not implement the full 8 a/d channels; the unimplemented selections are reserved. do not select any unimplemented channel. bit 2 go/done : a/d conversion status bit when adon = 1: 1 = a/d conversion in progress (setting this bit starts the a/d conversi on which is automatically cleared by hardware when the a/d conversion is complete) 0 = a/d conversion not in progress bit 1 unimplemented: read as '0' bit 0 adon: a/d on bit 1 = a/d converter module is powered up 0 = a/d converter module is shut-o ff and consumes no operating current legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown adcon1 adcon0 clock conversion 0 00 f osc /2 0 01 f osc /8 0 10 f osc /32 0 11 f rc (clock derived from the internal a/d rc oscillator) 1 00 f osc /4 1 01 f osc /16 1 10 f osc /64 1 11 f rc (clock derived from the internal a/d rc oscillator)
pic18cxx2 ds39026d-page 166 ? 1999-2013 microchip technology inc. register 16-2: adcon1 register r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7 adfm: a/d result format select bit 1 = right justified. six (6) most significant bits of adresh are read as ?0?. 0 = left justified. six (6) least significant bits of adresl are read as ?0?. bit 6 adcs2: a/d conversion clock select bit (adcon1 bits in bold ) bit 5-4 unimplemented: read as '0' bit 3-0 pcfg3:pcfg0: a/d port configuration control bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: on any device reset, the port pins that are multiplexed with analog functions (anx) are forced to be an analog input. adcon1 adcon0 clock conversion 0 00 f osc /2 0 01 f osc /8 0 10 f osc /32 0 11 f rc (clock derived from the internal a/d rc oscillator) 1 00 f osc /4 1 01 f osc /16 1 10 f osc /64 1 11 f rc (clock derived from the internal a/d rc oscillator) a = analog input d = digital i/o c/r = # of analog input channels/# of a/d voltage references pcfg an7 an6 an5 an4 an3 an2 an1 an0 v ref +v ref - c / r 0000 a a a a a a a a v dd v ss 8 / 0 0001 a a a a v ref +a a aan3v ss 7 / 1 0010 d d d a a a a a v dd v ss 5 / 0 0011 d d d a v ref +a a aan3v ss 4 / 1 0100 d d d d a d a a v dd v ss 3 / 0 0101 d d d d v ref +d a aan3v ss 2 / 1 011x d d d d d d d d ? ? 0 / 0 1000 a a a a v ref +v ref - a a an3 an2 6 / 2 1001 d d a a a a a a v dd v ss 6 / 0 1010 d d a a v ref +a a aan3v ss 5 / 1 1011 d d a a v ref +v ref - a a an3 an2 4 / 2 1100 d d d a v ref +v ref - a a an3 an2 3 / 2 1101 d d d d v ref +v ref - a a an3 an2 2 / 2 1110 d d d d d d d a v dd v ss 1 / 0 1111 d d d d v ref +v ref - d a an3 an2 1 / 2
? 1999-2013 microchip technology inc. ds39026d-page 167 pic18cxx2 the analog reference voltage is software selectable to either the device?s positive and negative supply voltage (v dd and v ss ) or the voltage level on the ra3/an3/ v ref + pin and ra2/an2/v ref -. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion is aborted. each port pin associated with the a/d converter can be configured as an analog input (ra3 can also be a volt- age reference) or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is complete, the result is loaded into the adresh/ adresl registers, the go/done bit (adcon0<2>) is cleared, and a/d interrupt flag bit adif is set. the block diagram of the a/d module is shown in figure 16-1. figure 16-1: a/d block diagram (input voltage) v ain v ref + reference voltage v dd pcfg0 chs2:chs0 an7 an6 an5 an4 an3 an2 an1 an0 111 110 101 100 011 010 001 000 10-bit converter v ref - v ss a/d
pic18cxx2 ds39026d-page 168 ? 1999-2013 microchip technology inc. the value that is in the adresh/adresl registers is not modified for a power-on reset. the adresh/ adresl registers will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 16.1. after this acquisition time has elapsed, the a/d conver- sion can be started. the following steps should be fol- lowed for doing an a/d conversion: 1. configure the a/d module: ? configure analog pins, voltage reference and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d conversion clock (adcon0) ? turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): ? clear adif bit ? set adie bit ? set gie bit 3. wait the required acquisition time. 4. start conversion: ? set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 6. read a/d result registers (adresh/adresl); clear bit adif if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2t ad is required before next acquisition starts. 16.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 16-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k ? . after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. figure 16-2: analog input model note: when the conversion is started, the hold- ing capacitor is disconnected from the input pin. v ain c pin rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic ? 1k sampling switch ss r ss c hold = 120 pf v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd 500 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
? 1999-2013 microchip technology inc. ds39026d-page 169 pic18cxx2 to calculate the minimum acquisition time, equation 16-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. equation 16-1: a cquisition time equation 16-2: a/d minimum charging time example 16-1 shows the calculation of the minimum required acquisition time t acq . this calculation is based on the following application system assump- tions: ?c hold = 120 pf ?rs = 2.5 k ?? ? conversion error ? 1/2 lsb ?v dd = 5v ? rss = 7 k ? ? temperature = 50 ? c (system max.) ?v hold = 0v @ time = 0 example 16-1: calculating the minimu m required acquisition time t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref - (v ref /2048)) ? (1 - e (-tc/c hold (r ic + r ss + r s )) ) or t c = -(120 pf)(1 k ? + r ss + r s ) ln(1/2047) t acq =t amp + t c + t coff temperature coefficient is only required for temperatures > 25 ? c. t acq =2 ? s + tc + [(temp - 25 ? c)(0.05 ? s/ ? c)] t c =-c hold (r ic + r ss + r s ) ln(1/2047) -120 pf (1 k ? + 7 k ? + 2.5 k ? ) ln(0.0004885) -120 pf (10.5 k ? ) ln(0.0004885) -1.26 ? s (-7.6241) 9.61 ? s t acq =2 ? s + 9.61 ? s + [(50 ? c - 25 ? c)(0.05 ? s/ ? c)] 11.61 ? s + 1.25 ? s 12.86 ? s
pic18cxx2 ds39026d-page 170 ? 1999-2013 microchip technology inc. 16.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 12 t ad per 10-bit conversion. the source of the a/d conversion clock is software selectable. the seven possible options for t ad are: ?2t osc ?4t osc ?8t osc ?16t osc ?32t osc ?64t osc ? internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 ? s. table 16-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. 16.3 configuring analog port pins the adcon1, trisa and trise registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. table 16-1: t ad vs. device operating frequencies table 16-2: t ad vs. device operating frequencies (for extended, lc, devices) note 1: when reading the port register, all pins con- figured as analog input channels will read as cleared (a low level). pins configured as dig- ital inputs will convert an analog input. ana- log levels on a digitally configured input will not affect the conversion accuracy. 2: analog levels on any pin that is defined as a digital input (including the an4:an0 pins) may cause the input buffer to con- sume current that is out of the devices specification. ad clock source (t ad ) device frequency operation adcs2:adcs0 40 mhz 20 mhz 5 mhz 1.25 mhz 333.33 khz 2t osc 000 50 ns 100 ns (2) 400 ns (2) 1.6 ? s6 ? s 4t osc 100 100 ns 200 ns (2) 800 ns (2) 3.2 ? s12 ? s 8t osc 001 200 ns 400 ns (2) 1.6 ? s6.4 ? s 24 ? s (3) 16t osc 101 400 ns 800 ns (2) 3.2 ? s12.8 ? s 48 ? s (3) 32t osc 010 800 ns 1.6 ? s6.4 ? s 25.6 ? s (3) 96 ? s (3) 64t osc 110 1.6 ? s3.2 ? s12.8 ? s 51.2 ? s (3) 192 ? s (3) rc 011 2 - 6 ? s (1) 2 - 6 ? s (1) 2 - 6 ? s (1) 2 - 6 ? s (1) 2 - 6 ? s (1) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 4 ? s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. ad clock source (t ad ) device frequency operation adcs2:adcs0 4 mhz 2 mhz 1.25 mhz 333.33 khz 2t osc 000 500 ns (2) 1.0 ? s (2) 1.6 ? s (2) 6 ? s 4t osc 100 1.0 ? s (2) 2.0 ? s (2) 3.2 ? s (2) 12 ? s 8t osc 001 2.0 ? s (2) 4.0 ? s6.4 ? s 24 ? s (3) 16t osc 101 4.0 ? s (2) 8.0 ? s 12.8 ? s 48 ? s (3) 32t osc 010 8.0 ? s16.0 ? s 25.6 ? s (3) 96 ? s (3) 64t osc 110 16.0 ? s32.0 ? s 51.2 ? s (3) 192 ? s (3) rc 011 3 - 9 ? s (1,4) 3 - 9 ? s (1,4) 3 - 9 ? s (1,4) 3 - 9 ? s (1,4) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 6 ? s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended.
? 1999-2013 microchip technology inc. ds39026d-page 171 pic18cxx2 16.4 a/d conversions figure 16-3 shows the operation of the a/d converter after the go bit has been set. clearing the go/done bit during a conversion will abort the current conver- sion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. that is, the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl reg- isters). after the a/d conversion is aborted, a 2t ad wait is required before the next acquisition is started. after this 2t ad wait, acquisition on the selected channel is automatically started. 16.5 use of the ccp2 trigger an a/d conversion can be started by the ?special event trigger? of the ccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be pro- grammed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/ done bit will be set, starting the a/d conversion and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving adresh/adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the ?special event trigger? sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the ?special event trigger? will be ignored by the a/d mod- ule, but will still reset the timer1 (or timer3) counter. figure 16-3: a/d conversion t ad cycles note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) b9 b8 b7 b6 b5 b4 b3 b2 t ad 9 t ad 10 b1 b0 t cy - t ad next q4: adresh/adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0
pic18cxx2 ds39026d-page 172 ? 1999-2013 microchip technology inc. table 16-3: summary of a/d registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 pir2 ? ? ? ? bclif lvdif tmr3if ccp2if ---- 0000 ---- 0000 pie2 ? ? ? ? bclie lvdie tmr3ie ccp2ie ---- 0000 ---- 0000 ipr2 ? ? ? ? bclip lvdip tmr3ip ccp2ip ---- 0000 ---- 0000 adresh a/d result register xxxx xxxx uuuu uuuu adresl a/d result register xxxx xxxx uuuu uuuu adcon0 adcs1 adcs0 chs2 chs1 chs0 go/ done ?adon 0000 00-0 0000 00-0 adcon1 adfm adcs2 ? ? pcfg3 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 porta ? ra6 ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 trisa ? porta data direction register --11 1111 --11 1111 porte ? ? ? ? ?re2re1re0 ---- -000 ---- -000 late ? ? ? ? ? late2 late1 late0 ---- -xxx ---- -uuu trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, ? = unimplemented, read as '0'. shaded cells are not used for a/d conversion. note 1: the pspif, pspie and pspip bits are reserved on the pic18c2x2 devices. always maintain these bits clear.
? 1999-2013 microchip technology inc. ds39026d-page 173 pic18cxx2 17.0 low voltage detect in many applications, the ability to determine if the device voltage (v dd ) is below a specified voltage level is a desirable feature. a window of operation for the application can be created, where the application soft- ware can do ?housekeeping tasks? before the device voltage exits the valid operating range. this can be done using the low voltage detect module. this module is a software programmable circuitry, where a device voltage trip point can be specified. when the voltage of the device becomes lower then the specified point, an interrupt flag is set. if the interrupt is enabled, the program execution will branch to the inter- rupt vector address and the software can then respond to that interrupt source. the low voltage detect circuitry is completely under software control. this allows the circuitry to be ?turned off? by the software, which minimizes the current con- sumption for the device. figure 17-1 shows a possible application voltage curve (typically for batteries). over time, the device voltage decreases. when the device voltage equals voltage v a , the lvd logic generates an interrupt. this occurs at time t a . the application software then has the time, until the device voltage is no longer in valid operating range, to shut-down the system. voltage point v b is the minimum valid operating voltage specification. this occurs at time t b . the difference t b - t a is the total time for shut-down. figure 17-1: typical low voltage detect application the block diagram for the lvd module is shown in figure 17-2. a comparator uses an internally gener- ated reference voltage as the set point. when the selected tap output of the device voltage crosses the set point (is lower than), the lvdif bit is set. each node in the resistor divider represents a ?trip point? voltage. the ?trip point? voltage is the minimum supply voltage level at which the device can operate before the lvd module asserts an interrupt. when the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the 1.2v internal reference voltage generated by the voltage reference module. the comparator then generates an interrupt signal setting the lvdif bit. this voltage is software programmable to any one of 16 values (see figure 17-2). the trip point is selected by program- ming the lvdl3:lvdl0 bits (lvdcon<3:0>). time voltage v a v b t a t b v a = lvd trip point v b = minimum valid device operating voltage legend:
pic18cxx2 ds39026d-page 174 ? 1999-2013 microchip technology inc. figure 17-2: low voltage dete ct (lvd) block diagram the lvd module has an additional feature that allows the user to supply the trip voltage to the module from an external source. this mode is enabled when bits lvdl3:lvdl0 are set to 1111 . in this state, the com- parator input is multiplexed from the external input pin lvdin (figure 17-3). this gives flexibility, because it allows a user to config- ure the low voltage detect interrupt to occur at any voltage in the valid operating range. figure 17-3: low voltage detect (lvd ) with external input block diagram lvdif v dd 16 to 1 mux lvden lvd control register internally generated nominal reference voltage lvdin 1.2v lvd en lvd control 16 to 1 mux bgap boden lvden vxen lvdin register v dd v dd externally generated trip point
? 1999-2013 microchip technology inc. ds39026d-page 175 pic18cxx2 17.1 control register the low voltage detect control register controls the operation of the low voltage detect circuitry. register 17-1: lvdcon register u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5 irvst: internal reference voltage stable flag bit 1 = indicates that the low voltage detect logic will generate the interrupt flag at the specified voltage range 0 = indicates that the low voltage detect logic will not generate the interrupt flag at the specified voltage range and the lvd interrupt should not be enabled bit 4 lvden: low voltage detect power enable bit 1 = enables lvd, powers up lvd circuit 0 = disables lvd, powers down lvd circuit bit 3-0 lvdl3:lvdl0: low voltage detection limit bits 1111 = external analog input is used (input comes from the lvdin pin) 1110 = 4.5v min. - 4.77v max. 1101 = 4.2v min. - 4.45v max. 1100 = 4.0v min. - 4.24v max. 1011 = 3.8v min. - 4.03v max. 1010 = 3.6v min. - 3.82v max. 1001 = 3.5v min. - 3.71v max. 1000 = 3.3v min. - 3.50v max. 0111 = 3.0v min. - 3.18v max. 0110 = 2.8v min. - 2.97v max. 0101 = 2.7v min. - 2.86v max. 0100 = 2.5v min. - 2.65v max. 0011 = 2.4v min. - 2.54v max. 0010 = 2.2v min. - 2.33v max. 0001 = 2.0v min. - 2.12v max. 0000 = 1.8v min. - 1.91v max. note: lvdl3:lvdl0 modes which result in a trip point below the valid operating voltage of the device are not tested. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset
pic18cxx2 ds39026d-page 176 ? 1999-2013 microchip technology inc. 17.2 operation depending on the power source for the device voltage, the voltage normally decreases relatively slowly. this means that the lvd module does not need to be con- stantly operating. to decrease the current require- ments, the lvd circuitry only needs to be enabled for short periods, where the voltage is checked. after doing the check, the lvd module may be disabled. each time that the lvd module is enabled, the circuitry requires some time to stabilize. after the circuitry has stabilized, all status flags may be cleared. the module will then indicate the proper state of the system. the following steps are needed to set up the lvd module: 1. write the value to the lvdl3:lvdl0 bits (lvd- con register), which selects the desired lvd trip point. 2. ensure that lvd interrupts are disabled (the lvdie bit is cleared, or the gie bit is cleared). 3. enable the lvd module (set the lvden bit in the lvdcon register). 4. wait for the lvd module to stabilize (the irvst bit to become set). 5. clear the lvd interrupt flag, which may have falsely become set until the lvd module has stabilized (clear the lvdif bit). 6. enable the lvd interrupt (set the lvdie and the gie bits). figure 17-4 shows typical waveforms that the lvd module may be used to detect. figure 17-4: low voltage detect waveforms v lvd v dd lvdif v lvd v dd enable lvd internally generated 50 ms lvdif may not be set enable lvd 50 ms lvdif lvdif cleared in software lvdif cleared in software lvdif cleared in software, case 1: case 2: lvdif remains set since lvd condition still exists reference stable internally generated reference stable
? 1999-2013 microchip technology inc. ds39026d-page 177 pic18cxx2 17.2.1 reference voltage set point the internal reference voltage of the lvd module may be used by other internal circuitry (the programmable brown-out reset). if these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low voltage condition can be reliably detected. this time is invariant of system clock speed. this start-up time is specified in electrical specification parameter #36. the low voltage interrupt flag will not be enabled until a stable reference voltage is reached. refer to the waveform in figure 17-4. 17.2.2 current consumption when the module is enabled, the lvd comparator and voltage divider are enabled and will consume static cur- rent. the voltage divider can be tapped from multiple places in the resistor array. total current consumption, when enabled, is specified in electrical specification parameter #d022b. 17.3 operation during sleep when enabled, the lvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the lvdif bit will be set and the device will wake- up from sleep. device execution will continue from the interrupt vector address, if interrupts have been glo- bally enabled. 17.4 effects of a reset a device reset forces all registers to their reset state. this forces the lvd module to be turned off.
pic18cxx2 ds39026d-page 178 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 179 pic18cxx2 18.0 special features of the cpu there are several features intended to maximize sys- tem reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. these are: ? osc selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming all pic18cxx2 devices have a watchdog timer, which is permanently enabled via the configuration bits or software-controlled. it runs off its own rc oscillator for added reliability. there are two timers that offer neces- sary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power- up timer (pwrt), which provides a fixed delay on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two tim- ers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost, while the lp crystal option saves power. a set of configuration bits are used to select various options. 18.1 configuration bits the configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. these bits are mapped starting at program memory location 300000h. the user will note that address 300000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (300000h - 3fffffh), which can only be accessed using table reads and table writes. table 18-1: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300000h config1l cp cp cp cp cp cp cp cp 1111 1111 300001h config1h ? ? oscsen ? ? fosc2 fosc1 fosc0 111- -111 300002h config2l ? ? ? ? borv1 borv0 boden pwrten ---- 1111 300003h config2h ? ? ? ? wdtps2 wdtps1 wdtps0 wdten ---- 1111 300005h config3h ? ? ? ? ? ? ? ccp2mx ---- ---1 300006h config4l ? ? ? ? ? ? lven stvren ---- --11 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 0000 0000 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0000 0010 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. shaded cells are unimplemented, read as ?0?
pic18cxx2 ds39026d-page 180 ? 1999-2013 microchip technology inc. register 18-1: configuration register 1 high (config1h: byte address 300001h) register 18-2: config uration register 1 low (config1l: byte address 300000h) r/p-1 r/p-1 r/p-1 u-0 u-0 r/p-1 r/p-1 r/p-1 reserved reserved oscsen ? ? fosc2 fosc1 fosc0 bit 7 bit 0 bit 7-6 reserved: read as ?1? bit 5 oscsen : oscillator system clock switch enable bit 1 = oscillator system clock switch option is disabled (main oscillator is source) 0 = oscillator system clock switch option is enabled (oscillator switching is enabled) bit 4-3 unimplemented: read as ?0? bit 2-0 fosc2:fosc0 : oscillator selection bits 111 = rc oscillator w/osc2 configured as ra6 110 = hs oscillator with pll enabled/clock frequency = (4 x f osc ) 101 = ec oscillator w/osc2 configured as ra6 100 = ec oscillator w/osc2 configured as divide-by-4 clock output 011 = rc oscillator 010 = hs oscillator 001 = xt oscillator 000 = lp oscillator legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 cp cp cp cp cp cp cp cp bit 7 bit 0 bit 7-0 cp: code protection bits (apply when in code protected microcontroller mode) 1 = program memory code protection off 0 = all of program memory code protected legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state
? 1999-2013 microchip technology inc. ds39026d-page 181 pic18cxx2 register 18-3: config uration register 2 high (config2h: byte address 300003h) register 18-4: configuration register 2 low (config2l: byte address 300002h) u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? wdtps2 wdtps1 wdtps0 wdten bit 7 bit 0 bit 7-4 unimplemented: read as ?0? bit 3-1 wdtps2:wdtps0: watchdog timer postscale select bits 111 = 1:1 110 = 1:2 101 = 1:4 100 = 1:8 011 = 1:16 010 = 1:32 001 = 1:64 000 = 1:128 bit 0 wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on the swdten bit) legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? borv1 borv0 boren pwrten bit 7 bit 0 bit 7-4 unimplemented: read as ?0? bit 3-2 borv1:borv0: brown-out reset voltage bits 11 = v bor set to 2.5v 10 = v bor set to 2.7v 01 = v bor set to 4.2v 00 = v bor set to 4.5v bit 1 boren: brown-out reset enable bit (1) 1 = brown-out reset enabled 0 = brown-out reset disabled note: enabling brown-out reset automatically enables the power-up timer (pwrt), regardless of the value of bit pwrten . ensure the power-up timer is enabled any time brown-out reset is enabled. bit 0 pwrten : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled note: enabling brown-out reset automatically enables the power-up timer (pwrt), regardless of the value of bit pwrte . ensure the power-up timer is enabled any time brown-out reset is enabled. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state
pic18cxx2 ds39026d-page 182 ? 1999-2013 microchip technology inc. register 18-5: config uration register 3 high (config3h: byte address 300005h) register 18-6: configuration register 4 low (config4l: byte address 300006h) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/p-1 ? ? ? ? ? ? ? ccp2mx bit 7 bit 0 bit 7-1 unimplemented: read as ?0? bit 0 ccp2mx: ccp2 mux bit 1 = ccp2 input/output is multiplexed with rc1 0 = ccp2 input/output is multiplexed with rb3 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state u-0 u-0 u-0 u-0 u-0 u-0 r/p-1 r/p-1 ? ? ? ? ? ? reserved stvren bit 7 bit 0 bit 7-2 unimplemented: read as ?0? bit 1 reserved: maintain this bit set bit 0 stvren: stack full/underflow reset enable bit 1 = stack full/underflow will cause reset 0 = stack full/underflow will not cause reset legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state
? 1999-2013 microchip technology inc. ds39026d-page 183 pic18cxx2 18.2 watchdog timer (wdt) the watchdog timer is a free running, on-chip rc oscillator, which does not require any external compo- nents. this rc oscillator is separate from the rc oscil- lator of the osc1/clki pin. that means that the wdt will run, even if the clock on the osc1/clki and osc2/ clko/ra6 pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the rcon register will be cleared upon a wdt time-out. the watchdog timer is enabled/disabled by a device configuration bit. if the wdt is enabled, software exe- cution may not disable this function. when the wdten configuration bit is cleared, the swdten bit enables/ disables the operation of the wdt. the wdt time-out period values may be found in the electrical specifications section under parameter #31. values for the wdt postscaler may be assigned using the configuration bits. 18.2.1 control register register 18-7 shows the wdtcon register. this is a readable and writable register, which contains a control bit that allows software to override the wdt enable configuration bit, only when the configuration bit has disabled the wdt. register 18-7: wdtcon register note: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset condition. note: when a clrwdt instruction is executed and the postscaler is assigned to the wdt, the postscaler count will be cleared, but the postscaler assignment is not changed. u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?swdten bit 7 bit 0 bit 7-1 unimplemented : read as ?0? bit 0 swdten: software controlled watchdog timer enable bit 1 = watchdog timer is on 0 = watchdog timer is turned off if the wdten configuration bit in the configuration register = ?0? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por reset
pic18cxx2 ds39026d-page 184 ? 1999-2013 microchip technology inc. 18.2.2 wdt postscaler the wdt has a postscaler that can extend the wdt reset period. the postscaler is selected at the time of device programming, by the value written to the config2h configuration register. figure 18-1: watchdog timer block diagram table 18-2: summary of watchdog timer registers postscaler wdt timer wdten 8 - to - 1 mux wdtps2:wdtps0 wdt time-out 8 swdten bit configuration bit note: wdps2:wdps0 are bits in register config2h. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 config2h ? ? ? ? wdtps2 wdtps2 wdtps0 wdten rcon ipen lwrt ? ri to pd por bor wdtcon ? ? ? ? ? ? ?swdten legend: shaded cells are not used by the watchdog timer.
? 1999-2013 microchip technology inc. ds39026d-page 185 pic18cxx2 18.3 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared, but keeps running, the pd bit (rcon<3>) is cleared, the to (rcon<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d and disable external clocks. pull all i/o pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). 18.3.1 wake-up from sleep the device can wake up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change, or a peripheral interrupt. the following peripheral interrupts can wake the device from sleep: 1. psp read or write. 2. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 3. tmr3 interrupt. timer3 must be operating as an asynchronous counter. 4. ccp capture mode interrupt. 5. special event trigger (timer1 in asynchronous mode using an external clock). 6. mssp (start/stop) bit detect interrupt. 7. mssp transmit or receive in slave mode (spi/i 2 c). 8. usart rx or tx (synchronous slave mode). 9. a/d conversion (when a/d clock source is rc). other peripherals cannot generate interrupts, since during sleep, no on-chip clocks are present. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and will cause a ?wake-up?. the to and pd bits in the rcon register can be used to determine the cause of the device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared, if a wdt time-out occurred (and caused wake-up). when the sleep instruction is being executed, the next instruction (pc + 2) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 18.3.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if an interrupt condition (interrupt flag bit and inter- rupt enable bits are set) occurs before the execu- tion of a sleep instruction, the sleep instruction will complete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. ? if the interrupt condition occurs during or after the execution of a sleep instruction, the device will immediately wake up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction.
pic18cxx2 ds39026d-page 186 ? 1999-2013 microchip technology inc. figure 18-2: wake-up from sleep through interrupt (1,2) 18.4 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 18.5 id locations five memory locations (200000h - 200004h) are desig- nated as id locations, where the user can store check- sum or other code identification numbers. these locations are accessible during normal execution through the tblrd instruction or during program/verify. the id locations can be read when the device is code protected. 18.6 in-circuit serial programming pic18cxxx microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firm- ware to be programmed. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon<1>) gieh bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+2 pc+4 inst(pc) = sleep inst(pc - 1) inst(pc + 2) sleep processor in sleep interrupt latency (3) inst(pc + 4) inst(pc + 2) inst(0008h) inst(000ah) inst(0008h) dummy cycle pc + 4 0008h 000ah dummy cycle t ost (2) pc+4 note 1: xt, hs or lp oscillator mode assumed. 2: gie = '1' assumed. in this case, after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will con tinue in-line. 3: t ost = 1024t osc (drawing not to scale) this delay will not occur for rc and ec osc modes. 4: clkout is not available in these osc modes, but shown here for timing reference. note: microchip technology does not recom- mend code protecting windowed devices.
? 1999-2013 microchip technology inc. ds39026d-page 187 pic18cxx2 19.0 instruction set summary the pic18cxxx instruction set adds many enhance- ments to the previous pic instruction sets, while main- taining an easy migration from these pic mcu instruction sets. most instructions are a single program memory word (16-bits), but there are three instructions that require two program memory locations. each single word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: ? byte-oriented operations ? bit-oriented operations ? literal operations ? control operations the pic18cxxx instruction set summary in table 19-2 lists byte-oriented , bit-oriented , literal and control operations. table 19-1 shows the opcode field descrip- tions. most byte-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the destination of the result (specified by ?d?) 3. the accessed memory (specified by ?a?) the file register designator 'f' specifies which file regis- ter is to be used by the instruction. the destination designator ?d? specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the wreg register. if 'd' is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the bit in the file register (specified by ?b?) 3. the accessed memory (specified by ?a?) the bit field designator 'b' selects the number of the bit affected by the operation, while the file register desig- nator 'f' represents the number of the file in which the bit is located. the literal instructions may use some of the following operands: ? a literal value to be loaded into a file register (specified by ?k?) ? the desired fsr register to load the literal value into (specified by ?f?) ? no operand required (specified by ???) the control instructions may use some of the following operands: ? a program memory address (specified by ?n?) ? the mode of the call or return instructions (specified by ?s?) ? the mode of the table read and table write instructions (specified by ?m?) ? no operand required (specified by ???) all instructions are a single word, except for three dou- ble word instructions. these three instructions were made double word instructions so that all the required information is available in these 32-bits. in the second word, the 4 msb?s are 1?s. if this second word is exe- cuted as an instruction (by itself), it will execute as a nop . all single word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a nop . the double word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 ? s. if a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 ? s. two word branch instructions (if true) would take 3 ? s. figure 19-1 shows the general formats that the instruc- tions can have. all examples use the format ?nnh? to represent a hexadecimal number, where ?h? signifies a hexadeci- mal digit. the instruction set summary, shown in table 19-2, lists the instructions recognized by the microchip assembler (mpasm tm ). section 19.1 provides a description of each instruction.
pic18cxx2 ds39026d-page 188 ? 1999-2013 microchip technology inc. table 19-1: opcode field descriptions field description a ram access bit a = 0: ram location in access ram (bsr register is ignored) a = 1: ram bank is specified by bsr register bbb bit address within an 8-bit file register (0 to 7) bsr bank select register. used to select the current ram bank. d destination select bit; d = 0: store result in wreg, d = 1: store result in file register f. dest destination either the wreg register or the specified register file location f 8-bit register file address (0x00 to 0xff) fs 12-bit register file address (0x000 to 0x fff). this is the source address. fd 12-bit register file address (0x000 to 0x fff). this is the destination address. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) label label name mm the mode of the tblptr register for the table read and table write instructions only used with table read and table write instructions: * no change to register (such as tb lptr with table reads and writes) *+ post-increment register (such as tblptr with table reads and writes) *- post-decrement register (such as tblptr with table reads and writes) +* pre-increment register (such as tblptr with table reads and writes) n the relative address (2?s complement number) for rela tive branch instructions, or the direct address for call/branch and return instructions prodh product of multiply high byte prodl product of multiply low byte s fast call/return mode select bit. s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (fast mode) u unused or unchanged wreg working register (accumulator) x don't care (0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. tblptr 21-bit table pointer (points to a program memory location) tablat 8-bit table latch tos top-of-stack pc program counter pcl program counter low byte pch program counter high byte pclath program counter high byte latch pclatu program counter upper byte latch gie global interrupt enable bit wdt watchdog timer to time-out bit pd power-down bit c, dc, z, ov, n alu status bits carry, digit carry, zero, overflow, negative [ ] optional ( ) contents ? assigned to < > register bit field ? in the set of italics user defined term (font is courier)
? 1999-2013 microchip technology inc. ds39026d-page 189 pic18cxx2 figure 19-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call, goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 0x7f goto label 15 8 7 0 opcode n<7:0> (literal) 15 12 11 0 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc s
pic18cxx2 ds39026d-page 190 ? 1999-2013 microchip technology inc. table 19-2: pic18cxxx instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s , f d f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination)2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 bit-oriented file register operations bcf bsf btfsc btfss btg f, b, a f, b, a f, b, a f, b, a f, d, a bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff none none none none none 1, 2 1, 2 3, 4 3, 4 1, 2 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2 word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated.
? 1999-2013 microchip technology inc. ds39026d-page 191 pic18cxx2 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep n n n n n n n n n n, s ? ? n ? ? ? ? n s k s ? branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine1st word 2nd word clear watchdog timer decimal adjust wreg go to address1st word 2nd word no operation no operation (note 4) pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd table 19-2: pic18cxxx instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2 word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated.
pic18cxx2 ds39026d-page 192 ? 1999-2013 microchip technology inc. literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw k k k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg move literal (12-bit) 2nd word to fsrx 1st word move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment table write table write with post-increment table write with post-decrement table write with pre-increment 2 2 (5) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none table 19-2: pic18cxxx instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2 word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated.
? 1999-2013 microchip technology inc. ds39026d-page 193 pic18cxx2 19.1 instruction set addlw add literal to wreg syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (wreg) + k ? wreg status affected: n,ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of wreg are added to the 8-bit literal 'k' and the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to wreg example : addlw 0x15 before instruction wreg = 0x10 after instruction wreg = 0x25 addwf add wreg to f syntax: [ label ] addwf f [,d [,a] f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (wreg) + (f) ? dest status affected: n,ov, c, dc, z encoding: 0010 01da ffff ffff description: add wreg to register 'f'. if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in reg- ister 'f' (default). if ?a? is 0, the access bank will be selected. if ?a? is 1, the bsr is used. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : addwf reg, 0, 0 before instruction wreg = 0x17 reg = 0xc2 after instruction wreg = 0xd9 reg = 0xc2
pic18cxx2 ds39026d-page 194 ? 1999-2013 microchip technology inc. addwfc add wreg and carry bit to f syntax: [ label ] addwfc f [,d [,a] operands: 0 ? f ? 255 d ?? [0,1] a ?? [0,1] operation: (wreg) + (f) + (c) ? dest status affected: n,ov, c, dc, z encoding: 0010 00da ffff ffff description: add wreg, the carry flag and data memory location 'f'. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed in data memory location 'f'. if ?a? is 0, the access bank will be selected. if ?a? is 1, the bsr will not be overridden. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : addwfc reg, 0, 1 before instruction carry bit= 1 reg = 0x02 wreg = 0x4d after instruction carry bit= 0 reg = 0x02 wreg = 0x50 andlw and literal with wreg syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (wreg) .and. k ? wreg status affected: n,z encoding: 0000 1011 kkkk kkkk description: the contents of wreg are anded with the 8-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to wreg example : andlw 0x5f before instruction wreg = 0xa3 after instruction wreg = 0x03
? 1999-2013 microchip technology inc. ds39026d-page 195 pic18cxx2 andwf and wreg with f syntax: [ label ] andwf f [,d [,a] operands: 0 ? f ? 255 d ?? [0,1] a ?? [0,1] operation: (wreg) .and. (f) ? dest status affected: n,z encoding: 0001 01da ffff ffff description: the contents of wreg are and?ed with register 'f'. if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ?a? is 0, the access bank will be selected. if ?a? is 1, the bsr will not be overridden (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : andwf reg, 0, 0 before instruction wreg = 0x17 reg = 0xc2 after instruction wreg = 0x02 reg = 0xc2 bc branch if carry syntax: [ label ] bc n operands: -128 ? n ? 127 operation: if carry bit is ?1? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is ?1?, then the pro- gram will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal 'n' process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal 'n' process data no operation example : here bc 5 before instruction pc = address (here) after instruction if carry = 1; pc = address (here+12) if carry ? 0; pc = address (here+2)
pic18cxx2 ds39026d-page 196 ? 1999-2013 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b[,a] operands: 0 ? f ? 255 0 ? b ? 7 a ?? [0,1] operation: 0 ? f status affected: none encoding: 1001 bbba ffff ffff description: bit 'b' in register 'f' is cleared. if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example : bcf flag_reg, 7, 0 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bn branch if negative syntax: [ label ] bn n operands: -128 ? n ? 127 operation: if negative bit is ?1? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is ?1?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal 'n' process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal 'n' process data no operation example : here bn jump before instruction pc = address (here) after instruction if negative = 1; pc = address (jump) if negative ? 0; pc = address (here+2)
? 1999-2013 microchip technology inc. ds39026d-page 197 pic18cxx2 bnc branch if not carry syntax: [ label ] bnc n operands: -128 ? n ? 127 operation: if carry bit is ?0? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is ?0?, then the pro- gram will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal 'n' process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal 'n' process data no operation example : here bnc jump before instruction pc = address (here) after instruction if carry = 0; pc = address (jump) if carry ? 1; pc = address (here+2) bnn branch if not negative syntax: [ label ] bnn n operands: -128 ? n ? 127 operation: if negative bit is ?0? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is ?0?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal 'n' process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal 'n' process data no operation example : here bnn jump before instruction pc = address (here) after instruction if negative ? 0; pc = address (jump) if negative = 1; pc = address (here+2)
pic18cxx2 ds39026d-page 198 ? 1999-2013 microchip technology inc. bnov branch if not overflow syntax: [ label ] bnov n operands: -128 ? n ? 127 operation: if overflow bit is ?0? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is ?0?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal 'n' process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal 'n' process data no operation example : here bnov jump before instruction pc = address (here) after instruction if overflow = 0; pc = address (jump) if overflow ? 1; pc = address (here+2) bnz branch if not zero syntax: [ label ] bnz n operands: -128 ? n ? 127 operation: if zero bit is ?0? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is ?0?, then the pro- gram will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal 'n' process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal 'n' process data no operation example : here bnz jump before instruction pc = address (here) after instruction if zero = 0; pc = address (jump) if zero ? 1; pc = address (here+2)
? 1999-2013 microchip technology inc. ds39026d-page 199 pic18cxx2 bra unconditional branch syntax: [ label ] bra n operands: -1024 ? n ? 1023 operation: (pc) + 2 + 2n ? pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is a two- cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'n' process data write to pc no operation no operation no operation no operation example : here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: [ label ] bsf f,b[,a] operands: 0 ? f ? 255 0 ? b ? 7 a ?? [0,1] operation: 1 ? f status affected: none encoding: 1000 bbba ffff ffff description: bit 'b' in register 'f' is set. if ?a? is 0 access bank will be selected, over- riding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example : bsf flag_reg, 7, 1 before instruction flag_reg= 0x0a after instruction flag_reg= 0x8a
pic18cxx2 ds39026d-page 200 ? 1999-2013 microchip technology inc. btfsc bit test file, skip if clear syntax: [ label ] btfsc f,b[,a] operands: 0 ? f ? 255 0 ? b ? 7 a ?? [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit 'b' in register ?f' is 0, then the next instruction is skipped. if bit 'b' is 0, then the next instruction fetched during the current instruction execution is discarded, and a nop is executed instead, making this a two- cycle instruction. if ?a? is 0, the access bank will be selected, over- riding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfsc : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false) btfss bit test file, skip if set syntax: [ label ] btfss f,b[,a] operands: 0 ? f ? 255 0 ? b < 7 a ?? [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit 'b' in register 'f' is 1 then the next instruction is skipped. if bit 'b' is 1, then the next instruction fetched during the current instruc- tion execution, is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is 0, the access bank will be selected, over- riding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfss : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true)
? 1999-2013 microchip technology inc. ds39026d-page 201 pic18cxx2 btg bit toggle f syntax: [ label ] btg f,b[,a] operands: 0 ? f ? 255 0 ? b < 7 a ?? [0,1] operation: (f ) ? f status affected: none encoding: 0111 bbba ffff ffff description: bit 'b' in data memory location 'f' is inverted. if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example : btg portc, 4, 0 before instruction: portc = 0111 0101 [0x75] after instruction: portc = 0110 0101 [0x65] bov branch if overflow syntax: [ label ] bov n operands: -128 ? n ? 127 operation: if overflow bit is ?1? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is ?1?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal 'n' process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal 'n' process data no operation example : here bov jump before instruction pc = address (here) after instruction if overflow = 1; pc = address (jump) if overflow ? 0; pc = address (here+2)
pic18cxx2 ds39026d-page 202 ? 1999-2013 microchip technology inc. bz branch if zero syntax: [ label ] bz n operands: -128 ? n ? 127 operation: if zero bit is ?1? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is ?1?, then the pro- gram will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal 'n' process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal 'n' process data no operation example : here bz jump before instruction pc = address (here) after instruction if zero = 1; pc = address (jump) if zero ? 0; pc = address (here+2) call subroutine call syntax: [ label ] call k [,s] operands: 0 ? k ? 1048575 s ?? [0,1] operation: (pc) + 4 ? tos, k ? pc<20:1>, if s = 1 (wreg) ? ws, (status) ? statuss, (bsr) ? bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2m byte memory range. first, return address (pc+ 4) is pushed onto the return stack. if ?s? = 1, the w, status and bsr registers are also pushed into their respective shadow registers, ws, statuss and bsrs. if 's' = 0, no update occurs (default). then the 20-bit value ?k? is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'k'<7:0>, push pc to stack read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example : here call there,1 before instruction pc = address(here) after instruction pc = address(there) tos = address (here + 4) ws = wreg bsrs= bsr statuss = status
? 1999-2013 microchip technology inc. ds39026d-page 203 pic18cxx2 clrf clear f syntax: [ label ] clrf f [,a] operands: 0 ? f ? 255 a ?? [0,1] operation: 000h ? f 1 ? z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example : clrf flag_reg,1 before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 000h ? wdt, 000h ? wdt postscaler, 1 ? to, 1 ? pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the postscaler of the wdt. status bits to and pd are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example : clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt postscaler = 0 to =1 pd =1
pic18cxx2 ds39026d-page 204 ? 1999-2013 microchip technology inc. comf complement f syntax: [ label ] comf f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: ? dest status affected: n,z encoding: 0001 11da ffff ffff description: the contents of register 'f' are com- plemented. if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : comf reg, 0, 0 before instruction reg = 0x13 after instruction reg = 0x13 wreg = 0xec (f) cpfseq compare f with wreg, skip if f = wreg syntax: [ label ] cpfseq f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: (f) ? (wreg), skip if (f) = (wreg) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location 'f' to the contents of wreg by performing an unsigned subtraction. if 'f' = wreg , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is 0, the access bank will be selected, over- riding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfseq reg, 0 nequal : equal : before instruction pc address = here wreg = ? reg = ? after instruction if reg = wreg; pc = address (equal) if reg ?? wreg; pc = address (nequal)
? 1999-2013 microchip technology inc. ds39026d-page 205 pic18cxx2 cpfsgt compare f with wreg, skip if f > wreg syntax: [ label ] cpfsgt f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: (f) ??? wreg), skip if (f) > (wreg) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location 'f' to the contents of the wreg by performing an unsigned subtraction. if the contents of 'f' are greater than the contents of wreg , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfsgt reg, 0 ngreater : greater : before instruction pc = address (here) wreg = ? after instruction if reg > wreg; pc = address (greater) if reg ? wreg; pc = address (ngreater) cpfslt compare f with wreg, skip if f < wreg syntax: [ label ] cpfslt f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: (f) ? ?? wreg), skip if (f) < (wreg) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location 'f' to the contents of wreg by performing an unsigned subtraction. if the contents of 'f' are less than the contents of wreg, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is 0, the access bank will be selected. if ?a? is 1, the bsr will not be overridden (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfslt reg, 1 nless : less : before instruction pc = address (here) w= ? after instruction if reg < wreg; pc = address (less) if reg ? wreg; pc = address (nless)
pic18cxx2 ds39026d-page 206 ? 1999-2013 microchip technology inc. daw decimal adjust wreg register syntax: [ label ] daw operands: none operation: if [wreg<3:0> >9] or [dc = 1] then (wreg<3:0>) + 6 ? wreg<3:0>; else ( wreg<3:0>) ? wreg<3:0>; if [wreg<7:4> >9] or [c = 1] then ( wreg<7:4>) + 6 ? wreg<7:4>; else (wreg<7:4>) ? wreg<7:4>; status affected: c encoding: 0000 0000 0000 0111 description: daw adjusts the eight-bit value in wreg, resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register wreg process data write wreg example1 : daw before instruction wreg = 0xa5 c=0 dc = 0 after instruction wreg = 0x05 c=1 dc = 0 example 2 : before instruction wreg = 0xce c=0 dc = 0 after instruction wreg = 0x34 c=1 dc = 0 decf decrement f syntax: [ label ] decf f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? 1 ? dest status affected: c,dc,n,ov,z encoding: 0000 01da ffff ffff description: decrement register 'f'. if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : decf cnt, 1, 0 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1
? 1999-2013 microchip technology inc. ds39026d-page 207 pic18cxx2 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f [,d [,a]] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? 1 ? dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register 'f' are decremented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is 0, the next instruc- tion, which is already fetched, is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here decfsz cnt, 1, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1 if cnt = 0; pc = address (continue) if cnt ? 0; pc = address (here+2) dcfsnz decrement f, skip if not 0 syntax: [ label ] dcfsnz f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? 1 ? dest, skip if result ? 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register 'f' are dec- remented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is not 0, the next instruction, which is already fetched, is discarded and a nop is executed instead, making it a two- cycle instruction. if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here dcfsnz temp, 1, 0 zero : nzero : before instruction temp = ? after instruction temp = temp - 1, if temp = 0; pc = address (zero) if temp ? 0; pc = address (nzero)
pic18cxx2 ds39026d-page 208 ? 1999-2013 microchip technology inc. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 1048575 operation: k ? pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2 mbyte memory range. the 20-bit value ?k? is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'k'<7:0>, no operation read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example : goto there after instruction pc = address (there) incf increment f syntax: [ label ] incf f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) + 1 ? dest status affected: c,dc,n,ov,z encoding: 0010 10da ffff ffff description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : incf cnt, 1, 0 before instruction cnt = 0xff z=0 c=? dc = ? after instruction cnt = 0x00 z=1 c=1 dc = 1
? 1999-2013 microchip technology inc. ds39026d-page 209 pic18cxx2 incfsz increment f, skip if 0 syntax: [ label ] incfsz f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) + 1 ? dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is 0, the next instruc- tion, which is already fetched, is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here incfsz cnt, 1, 0 nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address(zero) if cnt ? 0; pc = address(nzero) infsnz increment f, skip if not 0 syntax: [ label ] infsnz f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) + 1 ? dest, skip if result ? 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is not 0, the next instruction, which is already fetched, is discarded and a nop is executed instead, making it a two- cycle instruction. if ?a? is 0, the access bank will be selected, over- riding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here infsnz reg, 1, 0 zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg ? 0; pc = address (nzero) if reg = 0; pc = address (zero)
pic18cxx2 ds39026d-page 210 ? 1999-2013 microchip technology inc. iorlw inclusive or literal with wreg syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (wreg) .or. k ? wreg status affected: n,z encoding: 0000 1001 kkkk kkkk description: the contents of wreg are or?ed with the eight-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to wreg example : iorlw 0x35 before instruction wreg = 0x9a after instruction wreg = 0xbf iorwf inclusive or wreg with f syntax: [ label ] iorwf f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (wreg) .or. (f) ? dest status affected: n,z encoding: 0001 00da ffff ffff description: inclusive or wreg with register 'f'. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : iorwf result, 0, 1 before instruction result = 0x13 wreg = 0x91 after instruction result = 0x13 wreg = 0x93
? 1999-2013 microchip technology inc. ds39026d-page 211 pic18cxx2 lfsr load fsr syntax: [ label ] lfsr f,k operands: 0 ? f ? 2 0 ? k ? 4095 operation: k ? fsrf status affected: none encoding: 1110 1111 1110 0000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal 'k' is loaded into the file select register pointed to by 'f'. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'k' msb process data write literal 'k' msb to fsrfh decode read literal 'k' lsb process data write literal 'k' to fsrfl example : lfsr 2, 0x3ab after instruction fsr2h = 0x03 fsr2l = 0xab movf move f syntax: [ label ] movf f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: f ? dest status affected: n,z encoding: 0101 00da ffff ffff description: the contents of register 'f' are moved to a destination dependent upon the status of ?d?. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). location 'f' can be any- where in the 256 byte bank. if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write wreg example : movf reg, 0, 0 before instruction reg = 0x22 wreg = 0xff after instruction reg = 0x22 wreg = 0x22
pic18cxx2 ds39026d-page 212 ? 1999-2013 microchip technology inc. movff move f to f syntax: [ label ] movff f s ,f d operands: 0 ? f s ? 4095 0 ? f d ? 4095 operation: (f s ) ? f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff fff f s fff f d description: the contents of source register 'f s ' are moved to destination register 'f d '. location of source 'f s ' can be anywhere in the 4096 byte data space (000h to fffh), and location of destination 'f d ' can also be any- where from 000h to fffh. either source or destination can be wreg (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register. words: 2 cycles: 2 (3) q cycle activity: q1 q2 q3 q4 decode read register 'f' (src) process data no operation decode no operation no dummy read no operation write register 'f' (dest) example : movff reg1, reg2 before instruction reg1 = 0x33 reg2 = 0x11 after instruction reg1 = 0x33, reg2 = 0x33 movlb move literal to low nibble in bsr syntax: [ label ] movlb k operands: 0 ? k ? 255 operation: k ? bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the 8-bit literal 'k' is loaded into the bank select register (bsr). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write literal 'k' to bsr example : movlb 5 before instruction bsr register = 0x02 after instruction bsr register = 0x05
? 1999-2013 microchip technology inc. ds39026d-page 213 pic18cxx2 movlw move literal to wreg syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? wreg status affected: none encoding: 0000 1110 kkkk kkkk description: the eight-bit literal 'k' is loaded into wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to wreg example : movlw 0x5a after instruction wreg = 0x5a movwf move wreg to f syntax: [ label ] movwf f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: (wreg) ? f status affected: none encoding: 0110 111a ffff ffff description: move data from wreg to register 'f'. location 'f' can be anywhere in the 256 byte bank. if ?a? is 0, the access bank will be selected, over- riding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example : movwf reg, 0 before instruction wreg = 0x4f reg = 0xff after instruction wreg = 0x4f reg = 0x4f
pic18cxx2 ds39026d-page 214 ? 1999-2013 microchip technology inc. mullw multiply literal with wreg syntax: [ label ] mullw k operands: 0 ? k ? 255 operation: (wreg) x k ? prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is car- ried out between the contents of wreg and the 8-bit literal 'k'. the 16-bit result is placed in prodh:prodl register pair. prodh contains the high byte. wreg is unchanged. none of the status flags are affected. note that neither overflow, nor carry is possible in this opera- tion. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write registers prodh: prodl example : mullw 0xc4 before instruction wreg = 0xe2 prodh = ? prodl = ? after instruction wreg = 0xe2 prodh = 0xad prodl = 0x08 mulwf multiply wreg with f syntax: [ label ] mulwf f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: (wreg) x (f) ? prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is car- ried out between the contents of wreg and the register file loca- tion 'f'. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both wreg and 'f' are unchanged. none of the status flags are affected. note that neither overflow, nor carry is possible in this opera- tion. a zero result is possible but not detected. if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a?= 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write registers prodh: prodl example : mulwf reg, 1 before instruction wreg = 0xc4 reg = 0xb5 prodh = ? prodl = ? after instruction wreg = 0xc4 reg = 0xb5 prodh = 0x8a prodl = 0x94
? 1999-2013 microchip technology inc. ds39026d-page 215 pic18cxx2 negf negate f syntax: [ label ] negf f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: ( f ) + 1 ? f status affected: n,ov, c, dc, z encoding: 0110 110a ffff ffff description: location ?f? is negated using two?s complement. the result is placed in the data memory location 'f'. if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example : negf reg, 1 before instruction reg = 0011 1010 [0x3a] after instruction reg = 1100 0110 [0xc6] nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example : none.
pic18cxx2 ds39026d-page 216 ? 1999-2013 microchip technology inc. pop pop top of return stack syntax: [ label ] pop operands: none operation: (tos) ? bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previ- ous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example : pop goto new before instruction tos = 0031a2h stack (1 level down)= 014332h after instruction tos = 014332h pc = new push push top of return stack syntax: [ label ] push operands: none operation: (pc+2) ? tos status affected: none encoding: 0000 0000 0000 0101 description: the pc+2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows to implement a software stack by modifying tos, and then push it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc+2 onto return stack no operation no operation example : push before instruction tos = 00345ah pc = 000124h after instruction pc = 000126h tos = 000126h stack (1 level down) = 00345ah
? 1999-2013 microchip technology inc. ds39026d-page 217 pic18cxx2 rcall relative call syntax: [ label ] rcall n operands: -1024 ? n ? 1023 operation: (pc) + 2 ? tos, (pc) + 2 + 2n ? pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc+2) is pushed onto the stack. then, add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'n' push pc to stack process data write to pc no operation no operation no operation no operation example : here rcall jump before instruction pc = address(here) after instruction pc = address(jump) tos = address (here+2) reset reset syntax: [ label ] reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example : reset after instruction registers = reset value flags* = reset value
pic18cxx2 ds39026d-page 218 ? 1999-2013 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie [s] operands: s ? [0,1] operation: (tos) ? pc, 1 ? gie/gieh or peie/giel, if s = 1 (ws) ? wreg, (statuss) ? status, (bsrs) ? bsr, pclatu, pclath are unchanged. status affected: gie/gieh,peie/giel. encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting either the high or low priority global interrupt enable bit. if ?s? = 1, the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers, wreg, status and bsr. if ?s? = 0, no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example : retfie 1 after interrupt pc = tos w=ws bsr = bsrs status = statuss gie/gieh, peie/giel= 1 retlw return literal to wreg syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? wreg, (tos) ? pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: wreg is loaded with the eight-bit literal 'k'. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data pop pc from stack, write to wreg no operation no operation no operation no operation example : call table ; wreg contains table ; offset value ; wreg now has ; table value : table addwf pcl ; wreg = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction wreg = 0x07 after instruction wreg = value of kn
? 1999-2013 microchip technology inc. ds39026d-page 219 pic18cxx2 return return from subroutine syntax: [ label ] return [s] operands: s ? [0,1] operation: (tos) ? pc, if s = 1 (ws) ? wreg, (statuss) ? status, (bsrs) ? bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if ?s?= 1, the contents of the shadow registers ws, statuss and bsrs are loaded into their cor- responding registers, wreg, status and bsr. if ?s? = 0, no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example : return after interrupt pc = tos rlcf rotate left f through carry syntax: [ label ] rlcf f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? dest, (f<7>) ? c, (c) ? dest<0> status affected: c,n,z encoding: 0011 01da ffff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? = 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : rlcf reg, 0, 0 before instruction reg = 1110 0110 c=0 after instruction reg = 1110 0110 wreg = 1100 1100 c=1 c register f
pic18cxx2 ds39026d-page 220 ? 1999-2013 microchip technology inc. rlncf rotate left f (no carry) syntax: [ label ] rlncf f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? dest, (f<7>) ? dest<0> status affected: n,z encoding: 0100 01da ffff ffff description: the contents of register 'f' are rotated one bit to the left. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is stored back in reg- ister 'f' (default). if ?a? is 0, the access bank will be selected, over- riding the bsr value. if ?a? is 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : rlncf reg, 1, 0 before instruction reg = 1010 1011 after instruction reg = 0101 0111 register f rrcf rotate right f through carry syntax: [ label ] rrcf f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? dest, (f<0>) ? c, (c) ? dest<7> status affected: c,n,z encoding: 0011 00da ffff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? is 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : rrcf reg, 0, 0 before instruction reg = 1110 0110 c=0 after instruction reg = 1110 0110 wreg = 0111 0011 c=0 c register f
? 1999-2013 microchip technology inc. ds39026d-page 221 pic18cxx2 rrncf rotate right f (no carry) syntax: [ label ] rrncf f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? dest, (f<0>) ? dest<7> status affected: n,z encoding: 0100 00da ffff ffff description: the contents of register 'f' are rotated one bit to the right. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if ?a? is 0, the access bank will be selected, over- riding the bsr value. if ?a? is 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 : rrncf reg, 1, 0 before instruction reg = 1101 0111 after instruction reg = 1110 1011 example 2 : rrncf reg, 0, 0 before instruction wreg = ? reg = 1101 0111 after instruction wreg = 1110 1011 reg = 1101 0111 register f setf set f syntax: [ label ] setf f [,a] operands: 0 ? f ? 255 a ?? [0,1] operation: ffh ? f status affected: none encoding: 0110 100a ffff ffff description: the contents of the specified regis- ter are set to ffh. if ?a? is 0, the access bank will be selected, over- riding the bsr value. if ?a? is 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write register 'f' example : setf reg,1 before instruction reg = 0x5a after instruction reg = 0xff
pic18cxx2 ds39026d-page 222 ? 1999-2013 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt postscaler, 1 ? to , 0 ? pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example : sleep before instruction to =? pd =? after instruction to =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from wreg with borrow syntax: [ label ] subfwb f [,d [,a] operands: 0 ?? f ?? 255 d ? [0,1] a ? [0,1] operation: (wreg) ? (f) ? (c ) ?? dest status affected: n,ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register 'f' and carry flag (borrow) from wreg (2?s comple- ment method). if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored in register 'f' (default). if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? is 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 : subfwb reg, 1, 0 before instruction reg = 3 wreg = 2 c=1 after instruction reg = ff wreg = 2 c=0 z=0 n = 1 ; result is negative example 2 : subfwb reg, 0, 0 before instruction reg = 2 wreg = 5 c=1 after instruction reg = 2 wreg = 3 c=1 z=0 n = 0 ; result is positive example 3 : subfwb reg, 1, 0 before instruction reg = 1 wreg = 2 c=0 after instruction reg = 0 wreg = 2 c=1 z = 1 ; result is zero n=0
? 1999-2013 microchip technology inc. ds39026d-page 223 pic18cxx2 sublw subtract wreg from literal syntax: [ label ] sublw k operands: 0 ?? k ?? 255 operation: k ? (wreg) ?? wreg status affected: n,ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: wreg is subtracted from the eight-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to wreg example 1: sublw 0x02 before instruction wreg = 1 c=? after instruction wreg = 1 c = 1 ; result is positive z=0 n=0 example 2 : sublw 0x02 before instruction wreg = 2 c=? after instruction wreg = 0 c = 1 ; result is zero z=1 n=0 example 3 : sublw 0x02 before instruction wreg = 3 c=? after instruction wreg = ff ; (2?s complement) c = 0 ; result is negative z=0 n=1 subwf subtract wreg from f syntax: [ label ] subwf f [,d [,a] operands: 0 ?? f ?? 255 d ? [0,1] a ? [0,1] operation: (f) ? (wreg) ?? dest status affected: n,ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract wreg from register 'f' (2?s complement method). if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? is 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 : subwf reg, 1, 0 before instruction reg = 3 wreg = 2 c=? after instruction reg = 1 wreg = 2 c = 1 ; result is positive z=0 n=0 example 2 : subwf reg, 0, 0 before instruction reg = 2 wreg = 2 c=? after instruction reg = 2 wreg = 0 c = 1 ; result is zero z=1 n=0 example 3 : subwf reg, 1, 0 before instruction reg = 1 wreg = 2 c=? after instruction reg = ffh ;(2?s complement) wreg = 2 c = 0 ; result is negative z=0 n=1
pic18cxx2 ds39026d-page 224 ? 1999-2013 microchip technology inc. subwfb subtract wreg from f with borrow syntax: [ label ] subwfb f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? (wreg) ? (c ) ?? dest status affected: n,ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract wreg and the carry flag (borrow) from register 'f' (2?s comple- ment method). if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? is 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example 1 : subwfb reg, 1, 0 before instruction reg = 0x19 (0001 1001) wreg = 0x0d (0000 1101) c=1 after instruction reg = 0x0c (0000 1011) wreg = 0x0d (0000 1101) c=1 z=0 n = 0 ; result is positive example 2 : subwfb reg, 0, 0 before instruction reg = 0x1b (0001 1011) wreg = 0x1a (0001 1010) c=0 after instruction reg = 0x1b (0001 1011) wreg = 0x00 c=1 z = 1 ; result is zero n=0 example 3: subwfb reg, 1, 0 before instruction reg = 0x03 (0000 0011) wreg = 0x0e (0000 1101) c=1 after instruction reg = 0xf5 (1111 0100) ; [2?s comp] wreg = 0x0e (0000 1101) c=0 z=0 n = 1 ; result is negative swapf swap f syntax: [ label ] swapf f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f<3:0>) ? dest<7:4>, (f<7:4>) ? dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of reg- ister 'f' are exchanged. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed in register 'f' (default). if ?a? is 0, the access bank will be selected, overriding the bsr value. if ?a? is 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : swapf reg, 1, 0 before instruction reg = 0x53 after instruction reg = 0x35
? 1999-2013 microchip technology inc. ds39026d-page 225 pic18cxx2 tblrd table read syntax: [ label ] tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) ? tablat; tblptr - no change; if tblrd *+, (prog mem (tblptr)) ? tablat; (tblptr) +1 ? tblptr; if tblrd *-, (prog mem (tblptr)) ? tablat; (tblptr) -1 ? tblptr; if tblrd +*, (tblptr) +1 ? tblptr; (prog mem (tblptr)) ? tablat; status affected: none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2 mbyte address range. tblptr[0] = 0: least significant byte of program memory word tblptr[0] = 1: most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: ? no change ? post-increment ? post-decrement ? pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) tblrd table read (cont?d) example 1 : tblrd *+ ; before instruction tablat = 0x55 tblptr = 0x00a356 memory(0x00a356) = 0x34 after instruction tablat = 0x34 tblptr = 0x00a357 example 2 : tblrd +* ; before instruction tablat = 0xaa tblptr = 0x01a357 memory(0x01a357) = 0x12 memory(0x01a358) = 0x34 after instruction tablat = 0x34 tblptr = 0x01a358
pic18cxx2 ds39026d-page 226 ? 1999-2013 microchip technology inc. tblwt table write syntax: [ label ] tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) ? prog mem (tblptr) or holding register; tblptr - no change; if tblwt*+, (tablat) ? prog mem (tblptr) or holding register; (tblptr) +1 ? tblptr; if tblwt*-, (tablat) ? prog mem (tblptr) or holding register; (tblptr) -1 ? tblptr; if tblwt+*, (tblptr) +1 ? tblptr; (tablat) ? prog mem (tblptr) or holding register; status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to program the contents of program memory (p.m.). the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2 mbyte address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0:least significant byte of program memory word tblptr[0] = 1:most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: ? no change ? post-increment ? post-decrement ? pre-increment words: 1 cycles: 2 (many if long write is to on-chip eprom program memory) q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register or memory) tblwt table write (continued) example 1 : tblwt *+; before instruction tablat = 0x55 tblptr = 0x00a356 memory(0x00a356) = 0xff after instructions (table write completion) tablat = 0x55 tblptr = 0x00a357 memory(0x00a356) = 0x55 example 2 : tblwt +*; before instruction tablat = 0x34 tblptr = 0x01389a memory(0x01389a) = 0xff memory(0x01389b) = 0xff after instruction (table write completion) tablat = 0x34 tblptr = 0x01389b memory(0x01389a) = 0xff memory(0x01389b) = 0x34
? 1999-2013 microchip technology inc. ds39026d-page 227 pic18cxx2 tstfsz test f, skip if 0 syntax: [ label ] tstfsz f [,a] operands: 0 ? f ? 255 a ? [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if 'f' = 0, the next instruction, fetched during the current instruc- tion execution, is discarded and a nop is executed, making this a two- cycle instruction. if ?a? is 0, the access bank will be selected, over- riding the bsr value. if ?a? is 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register 'f' process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here tstfsz cnt, 1 nzero : zero : before instruction pc = address(here) after instruction if cnt = 0x00, pc = address (zero) if cnt ? 0x00, pc = address (nzero) xorlw exclusive or literal with wreg syntax: [ label ] xorlw k operands: 0 ?? k ?? 255 operation: (wreg) .xor. k ?? wreg status affected: n,z encoding: 0000 1010 kkkk kkkk description: the contents of wreg are xored with the 8-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal 'k' process data write to wreg example :xorlw0xaf before instruction wreg = 0xb5 after instruction wreg = 0x1a
pic18cxx2 ds39026d-page 228 ? 1999-2013 microchip technology inc. xorwf exclusive or wreg with f syntax: [ label ] xorwf f [,d [,a] operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (wreg) .xor. (f) ?? dest status affected: n,z encoding: 0001 10da ffff ffff description: exclusive or the contents of wreg with register 'f'. if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in the reg- ister 'f' (default). if ?a? is 0, the access bank will be selected, over- riding the bsr value. if ?a? is 1, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register 'f' process data write to destination example : xorwf reg, 1, 0 before instruction reg = 0xaf wreg = 0xb5 after instruction reg = 0x1a wreg = 0xb5
? 1999-2013 microchip technology inc. ds39026d-page 229 pic18cxx2 20.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - icepic? in-circuit emulator ? in-circuit debugger - mplab icd for pic16f87x ? device programmers -pro mate ? ii universal device programmer - picstart ? plus entry-level development programmer ? low cost demonstration boards - picdem tm 1 demonstration board - picdem 2 demonstration board - picdem 3 demonstration board - picdem 17 demonstration board -k ee l oq ? demonstration board 20.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. the mplab ide is a windows ? -based application that contains: ? an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor ? a project manager ? customizable toolbar and key mapping ? a status bar ? on-line help the mplab ide allows you to: ? edit your source files (either assembly or ?c?) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (auto- matically updates all project information) ? debug using: - source files - absolute listing file - machine code the ability to use mplab ide with multiple debugging tools allows users to easily switch from the cost- effective simulator to a full-featured emulator with minimal retraining. 20.2 mpasm assembler the mpasm assembler is a full-featured universal macro assembler for all pic mcus. the mpasm assembler has a command line interface and a windows shell. it can be used as a stand-alone application on a windows 3.x or greater system, or it can be used through mplab ide. the mpasm assem- bler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, an abso- lute lst file that contains source lines and generated machine code, and a cod file for debugging. the mpasm assembler features include: ? integration into mplab ide projects. ? user-defined macros to streamline assembly code. ? conditional assembly for multi-purpose source files. ? directives that allow complete control over the assembly process. 20.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi ?c? compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic18cxx2 ds39026d-page 230 ? 1999-2013 microchip technology inc. 20.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can also link relocatable objects from pre-compiled libraries, using directives from a linker script. the mplib object librarian is a librarian for pre- compiled code to be used with the mplink object linker. when a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the mplib object librarian manages the creation and modification of library files. the mplink object linker features include: ? integration with mpasm assembler and mplab c17 and mplab c18 c compilers. ? allows all memory areas to be defined as sections to provide link-time flexibility. the mplib object librarian features include: ? easier linking because single libraries can be included instead of many smaller files. ? helps keep code maintainable by grouping related modules together. ? allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. 20.5 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc-hosted environment by simulating the pic series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. the execu- tion can be performed in single step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debug- ging using the mplab c17 and the mplab c18 c com- pilers and the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. 20.6 mplab ice high performance universal in-circuit emulator with mplab ide the mplab ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic micro- controllers (mcus). software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment (ide), which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. the pc platform and microsoft ? windows environment were chosen to best make these features available to you, the end user. 20.7 icepic in-circuit emulator the icepic low cost, in-circuit emulator is a solution for the microchip technology pic16c5x, pic16c6x, pic16c7x and pic16cxxx families of 8-bit one- time-programmable (otp) microcontrollers. the mod- ular system can support different subsets of pic16c5x or pic16cxxx products through the use of inter- changeable personality modules, or daughter boards. the emulator is capable of emulating without target application circuitry being present.
? 1999-2013 microchip technology inc. ds39026d-page 231 pic18cxx2 20.8 mplab icd in-circuit debugger microchip's in-circuit debugger, mplab icd, is a pow- erful, low cost, run-time development tool. this tool is based on the flash pic16f87x and can be used to develop for this and other pic microcontrollers from the pic16cxxx family. the mplab icd utilizes the in-cir- cuit debugging capability built into the pic16f87x. this feature, along with microchip's in-circuit serial programming tm protocol, offers cost-effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. 20.9 pro mate ii universal device programmer the pro mate ii universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as pc-hosted mode. the pro mate ii device programmer is ce compliant. the pro mate ii device programmer has program- mable v dd and v pp supplies, which allow it to verify programmed memory at v dd min and v dd max for max- imum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, or program pic devices. it can also set code protection in this mode. 20.10 picstart plus entry level development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer sup- ports all pic devices with up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 20.11 picdem 1 low cost pic mcu demonstration board the picdem 1 demonstration board is a simple board which demonstrates the capabilities of several of microchip?s microcontrollers. the microcontrollers sup- ported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the user can program the sample microcon- trollers provided with the picdem 1 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the user can also connect the picdem 1 demonstration board to the mplab ice in- circuit emulator and download the firmware to the emu- lator for testing. a prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simu- lated analog input, push button switches and eight leds connected to portb. 20.12 picdem 2 low cost pic16cxx demonstration board the picdem 2 demonstration board is a simple dem- onstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and soft- ware is included to run the basic demonstration pro- grams. the user can program the sample microcontrollers provided with the picdem 2 demon- stration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 2 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding additional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a serial eeprom to demonstrate usage of the i 2 c tm bus and separate headers for connection to an lcd module and a keypad.
pic18cxx2 ds39026d-page 232 ? 1999-2013 microchip technology inc. 20.13 picdem 3 low cost pic16cxxx demonstration board the picdem 3 demonstration board is a simple dem- onstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with an lcd mod- ule. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers pro- vided with the picdem 3 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer with an adapter socket, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 3 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem 3 demonstration board is a lcd panel, with 4 commons and 12 segments, that is capable of display- ing time, temperature and day of the week. the picdem 3 demonstration board provides an additional rs-232 interface and windows software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. 20.14 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. all neces- sary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. a programmed sample is included and the user may erase it and program it with the other sample programs using the pro mate ii device programmer, or the picstart plus development programmer, and easily debug and test the sample code. in addition, the picdem 17 dem- onstration board supports downloading of programs to and executing out of external flash memory on board. the picdem 17 demonstration board is also usable with the mplab ice in-circuit emulator, or the picmaster emulator and all of the sample programs can be run and modified using either emulator. addition- ally, a generous prototype area is available for user hardware. 20.15 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchip?s hcs secure data products. the hcs eval- uation kit includes a lcd display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters.
? 1999-2013 microchip technology inc. ds39026d-page 233 pic18cxx2 table 20-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment ?????????????? mplab ? c17 c compiler ?? mplab ? c18 c compiler ? mpasm tm assembler/ mplink tm object linker ???????????????? emulators mplab ? ice in-circuit emulator ?????? ** ???????? icepic tm in-circuit emulator ? ??? ??? ? debugger mplab ? icd in-circuit debugger ? * ? * ? programmers picstart ? plus entry level development programmer ?????? ** ???????? pro mate ? ii universal device programmer ?????? ** ?????????? demo boards and eval kits picdem tm 1 demonstration board ??? ? ?? picdem tm 2 demonstration board ? ? ? ? ? picdem tm 3 demonstration board ? picdem tm 14a demonstration board ? picdem tm 17 demonstration board ? k ee l oq ? evaluation kit ? k ee l oq ? transponder kit ? microid tm programmer?s kit ? 125 khz microid tm developer?s kit ? 125 khz anticollision microid tm developer?s kit ? 13.56 mhz anticollision microid tm developer?s kit ? mcp2510 can developer?s kit ? * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77. ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic18cxx2 ds39026d-page 234 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 235 pic18cxx2 21.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-55c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr , and ra4) ....................................... -0.3 v to (v dd + 0.3 v) voltage on v dd with respect to v ss ....................................................................................................... -0.3 v to +7.5 v voltage on mclr with respect to v ss (note 2) ....................................................................................... 0 v to +13.25 v voltage on ra4 with respect to vss ............................................................................................. ................ 0 v to +8.5 v total power dissipation (note 1) ..............................................................................................................................1 .0 w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????? ? 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????? ? 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by ? porta, portb, and porte (note 3) (combined) ...................................................200 ma maximum current sourced by porta, portb, and porte (note 3) (combined)..............................................200 ma maximum current sunk by portc and portd (note 3) (combined)..................................................................200 ma maximum current sourced by portc and portd (note 3) (combined).............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ?low? level to the mclr /v pp pin, rather than pulling this pin directly to v ss . 3: portd and porte not available on the pic18c2x2 devices. ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic18cxx2 ds39026d-page 236 ? 1999-2013 microchip technology inc. figure 21-1: pic18cxx2 voltage-frequency graph (industrial, extended) figure 21-2: pic18lcxx2 voltage-freq uency graph (industrial) frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 40 mhz 5.0 v 3.5 v 3.0 v 2.5 v pic18cxxx 4.2v frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 40 mhz 5.0 v 3.5 v 3.0 v 2.5 v pic18lcxxx f max = (20.0 mhz/v) (v ddappmin - 2.5 v) + 6 mhz note: v ddappmin is the minimum voltage of the pic ? device in the application. 6 mhz 4.2v
? 1999-2013 microchip technology inc. ds39026d-page 237 pic18cxx2 21.1 dc characteristics pic18lcxx2 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18cxx2 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ max units conditions v dd supply voltage d001 pic18lcxx2 2.5 ? 5.5 v hs, xt, rc and lp osc mode d001 pic18cxx2 4.2 ? 5.5 v d002 v dr ram data retention voltage (1) 1.5 ? ? v d003 v por v dd start voltage to ensure internal power-on reset signal ? ? 0.7 v see section on power-on reset for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section on power-on reset for details v bor brown-out reset voltage d005 pic18lcxx2 borv1:borv0 = 11 2.5 ? 2.66 v borv1:borv0 = 10 2.7 ? 2.86 v borv1:borv0 = 01 4.2 ? 4.46 v borv1:borv0 = 00 4.5 ? 4.78 v d005 pic18cxx2 borv1:borv0 = 1x n.a. ? n.a. v not in operating voltage range of device borv1:borv0 = 01 4.2 ? 4.46 v borv1:borv0 = 00 4.5 ? 4.78 v legend: shading of rows is to assist in readability of the table. note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss , and all fea- tures that add delta current disabled (such as wdt, timer1 oscillator, bor,...). 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm.
pic18cxx2 ds39026d-page 238 ? 1999-2013 microchip technology inc. i dd supply current (2,4) d010 pic18lcxx2 ? ? 2 ma xt, rc, rcio osc configurations f osc = 4 mhz, v dd = 2.5v d010 pic18cxx2 ? ? 4 ma xt, rc, rcio osc configurations f osc = 4 mhz, v dd = 4.2v d010a pic18lcxx2 ? ? 55 ? a lp osc configuration f osc = 32 khz, v dd = 2.5v d010a pic18cxx2 ? ? 250 ? a lp osc configuration f osc = 32 khz, v dd = 4.2v d010c pic18lcxx2 ? ? 38 ma ec, ecio osc configurations f osc = 40 mhz, v dd = 5.5v d010c pic18cxx2 ? ? 38 ma ec, ecio osc configurations f osc = 40 mhz, v dd = 5.5v d013 pic18lcxx2 ? ? ? ? ? ? 3.5 25 38 ma ma ma hs osc configuration f osc = 6 mhz, v dd = 2.5v f osc = 25 mhz, v dd = 5.5v hs + pll osc configurations f osc = 10 mhz, v dd = 5.5v d013 pic18cxx2 ? ? ? ? 25 38 ma ma hs osc configuration f osc = 25 mhz, v dd = 5.5v hs + pll osc configurations f osc = 10 mhz, v dd = 5.5v d014 pic18lcxx2 ??55 ? a timer1 osc configuration f osc = 32 khz, v dd = 2.5v d014 pic18cxx2 ? ? ? ? 200 250 ? a ? a oscb osc configuration f osc = 32 khz, v dd = 4.2v, -40 ? c to +85 ? c f osc = 32 khz, v dd = 4.2v, -40 ? c to +125 ? c legend: shading of rows is to assist in readability of the table. note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss , and all fea- tures that add delta current disabled (such as wdt, timer1 oscillator, bor,...). 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 21.1 dc characteristics (continued) pic18lcxx2 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18cxx2 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ max units conditions
? 1999-2013 microchip technology inc. ds39026d-page 239 pic18cxx2 i pd power-down current (3) d020 pic18lcxx2 ? ? <.5 ? 2 4 ? a ? a v dd = 2.5v, -40 ? c to +85 ? c v dd = 5.5v, -40 ? c to +85 ? c d020 d021b pic18cxx2 ? ? ? ? <1 ? ? ? 3 4 15 20 ? a ? a ? a ? a v dd = 4.2v, -40 ? c to +85 ? c v dd = 5.5v, -40 ? c to +85 ? c v dd = 4.2v, -40 ? c to +125 ? c v dd = 5.5v, -40 ? c to +125 ? c module differential current d022 ? i wdt watchdog timer pic18lcxx2 ? ? ? ? 1 15 ? a ? a v dd = 2.5v v dd = 5.5v d022 watchdog timer pic18cxx2 ? ? ? ? 15 20 ? a ? a v dd = 5.5v, -40 ? c to +85 ? c v dd = 5.5v, -40 ? c to +125 ? c d022a ? i bor brown-out reset pic18lcxx2 ??45 ? av dd = 2.5v d022a brown-out reset pic18cxx2 ? ? ? ? 50 50 ? a ? a v dd = 5.5v, -40 ? c to +85 ? c v dd = 5.5v, -40 ? c to +125 ? d022b ? i lvd low voltage detect pic18lcxx2 ??45 ? av dd = 2.5v d022b low voltage detect pic18cxx2 ? ? ? ? 50 50 ? a ? a v dd = 4.2v, -40 ? c to +85 ? c v dd = 4.2v, -40 ? c to +125 ? c d025 ? i oscb timer1 oscillator pic18lcxx2 ??15 ? av dd = 2.5v d025 timer1 oscillator pic18cxx2 ? ? ? ? 100 120 ? a ? a v dd = 4.2v, -40 ? c to +85 ? c v dd = 4.2v, -40 ? c to +125 ? c legend: shading of rows is to assist in readability of the table. note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss , and all fea- tures that add delta current disabled (such as wdt, timer1 oscillator, bor,...). 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2r ext (ma) with r ext in kohm. 21.1 dc characteristics (continued) pic18lcxx2 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial pic18cxx2 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min typ max units conditions
pic18cxx2 ds39026d-page 240 ? 1999-2013 microchip technology inc. 21.2 dc characteristics: pic18cxx2 (industrial, extended) pic18lcxx2 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ? +85c for industrial -40c ?? t a ? +125c for extended param no. symbol characteristic min max units conditions v il input low voltage i/o ports: d030 with ttl buffer vss 0.15v dd vv dd < 4.5v d030a ? 0.8 v 4.5v ? v dd ?? 5.5v d031 with schmitt trigger buffer rc3 and rc4 vss vss 0.2v dd 0.3v dd v v d032 mclr v ss 0.2v dd v d032a osc1 (in xt, hs and lp modes) and t1osi v ss 0.3v dd v d033 osc1 (in rc and ec mode) (1) v ss 0.2v dd v v ih input high voltage i/o ports: d040 with ttl buffer 0.25v dd + 0.8v v dd vv dd < 4.5v d040a 2.0 v dd v4.5v ? v dd ?? 5.5v d041 with schmitt trigger buffer rc3 and rc4 0.8v dd 0.7v dd v dd v dd v v d042 mclr , osc1 (ec mode) 0.8v dd v dd v d042a osc1 (in xt, hs and lp modes) and t1osi 0.7v dd v dd v d043 osc1 (rc mode) (1) 0.9v dd v dd v i il input leakage current (2,3) d060 i/o ports ? ? 1 ? av ss ?? v pin ?? v dd , pin at hi-impedance d061 mclr ? ? 5 ? avss ?? v pin ?? v dd d063 osc1 ? ? 5 ? avss ?? v pin ?? v dd i pu weak pull-up current d070 i purb portb weak pull-up current 50 400 ? av dd = 5v, v pin = v ss note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic mcu be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
? 1999-2013 microchip technology inc. ds39026d-page 241 pic18cxx2 v ol output low voltage d080 i/o ports ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 ? c to +85 ? c d080a ? 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 ? c to +125 ? c d083 osc2/clkout (rc mode) ?0.6vi ol = 1.6 ma, v dd = 4.5v, -40 ? c to +85 ? c d083a ? 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 ? c to +125 ? c v oh output high voltage (3) d090 i/o ports v dd - 0.7 ? v i oh = -3.0 ma, v dd = 4.5v, -40 ? c to +85 ? c d090a v dd - 0.7 ? v i oh = -2.5 ma, v dd = 4.5v, -40 ? c to +125 ? c d092 osc2/clkout (rc mode) v dd - 0.7 ? v i oh = -1.3 ma, v dd = 4.5v, -40 ? c to +85 ? c d092a v dd - 0.7 ? v i oh = -1.0 ma, v dd = 4.5v, -40 ? c to +125 ? c d150 v od open drain high voltage ? 8.5 v ra4 pin capacitive loading specs on output pins d101 c io all i/o pins and osc2 (in rc mode) ? 50 pf to meet the ac timing specifications d102 c b scl, sda ? 400 pf in i 2 c mode 21.2 dc characteristics: pic18cxx2 (industrial, extended) pic18lcxx2 (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ? +85c for industrial -40c ?? t a ? +125c for extended param no. symbol characteristic min max units conditions note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic mcu be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic18cxx2 ds39026d-page 242 ? 1999-2013 microchip technology inc. figure 21-3: low voltage detect characteristics table 21-1: low voltage detect characteristics v lvd lvdif v dd (lvdif set by hardware) (lvdif can be cleared in software) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. symbol characteristic min max units conditions d420 v lvd lvd voltage lvv<3:0> = 0100 2.5 2.66 v lvv<3:0> = 0101 2.7 2.86 v lvv<3:0> = 0110 2.8 2.98 v lvv<3:0> = 0111 3.0 3.2 v lvv<3:0> = 1000 3.3 3.52 v lvv<3:0> = 1001 3.5 3.72 v lvv<3:0> = 1010 3.6 3.84 v lvv<3:0> = 1011 3.8 4.04 v lvv<3:0> = 1100 4.0 4.26 v lvv<3:0> = 1101 4.2 4.46 v lvv<3:0> = 1110 4.5 4.78 v
? 1999-2013 microchip technology inc. ds39026d-page 243 pic18cxx2 table 21-2: eprom programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +40c param. no. sym characteristic min max units conditions internal program memory programming specs (note 1) d110 v pp voltage on mclr /v pp pin 12.75 13.25 v (note 2) d111 v ddp supply voltage during programming 4.75 5.25 v d112 i pp current into mclr /v pp pin ? 50 ma d113 i ddp supply current during programming ?30ma d114 t prog programming pulse width 50 1000 ? s terminated via internal/external interrupt or a reset d115 t erase eprom erase time device operation ? 3v device operation ? 3v 60 30 ? ? min. min. note 1: these specifications are for the programming of the on-chip program memory eprom through the use of the table write instructions. the complete programming specifications can be found in the pic18cxxx programming specifications (literature number ds39028). 2: the mclr /v pp pin may be kept in this range at times other than programming, but is not recommended.
pic18cxx2 ds39026d-page 244 ? 1999-2013 microchip technology inc. 21.3 ac (timing) characteristics 21.3.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition
? 1999-2013 microchip technology inc. ds39026d-page 245 pic18cxx2 21.3.2 timing conditions the temperature and voltages specified in table 21-3 apply to all timing specifications unless otherwise noted. figure 21-4 specifies the load conditions for the timing specifications. table 21-3: temperature and voltage specifications - ac figure 21-4: load conditions for de vice timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended operating voltage v dd range as described in dc spec section 21.1. lc parts operate for industrial temperatures only. v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2/clkout and including d and e outputs as ports load condition 1 load condition 2
pic18cxx2 ds39026d-page 246 ? 1999-2013 microchip technology inc. 21.3.3 timing diagrams and specifications figure 21-5: external clock timing (all modes exce pt pll) table 21-4: external clock timing requirements osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 param. no. symbol characteristic min max units conditions 1a f osc external clkin frequency (1) dc 4 mhz xt osc dc 25 mhz hs osc 4 10 mhz hs + pll osc dc dc 40 40 khz mhz lp osc ec, ecio oscillator frequency (1) dc 4 mhz rc osc 0.1 4 mhz xt osc 4 25 mhz hs osc 4 10 mhz hs + pll osc 5 200 khz lp osc mode 1t osc external clkin period (1) 250 ? ns xt and rc osc 40 ? ns hs osc 100 250 ns hs + pll osc 25 25 ? ? ? s ns lp osc ec, ecio oscillator period (1) 250 ? ns rc osc 250 10,000 ns xt osc 25 100 250 250 ns ns hs osc hs + pll osc 25 ? ? slp osc 2t cy instruction cycle time (1) 100 ? ns t cy = 4/f osc 3 tosl, to s h external clock in (osc1) high or low time 30 ? ns xt osc 2.5 ? ? slp osc 10 ? ns hs osc 4tosr, to s f external clock in (osc1) rise or fall time ? 20 ns xt osc ? 50 ns lp osc ? 7.5 ns hs osc note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period for all configurations except pll. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices.
? 1999-2013 microchip technology inc. ds39026d-page 247 pic18cxx2 table 21-5: pll clock timing specification (v dd = 4.2v - 5.5v) figure 21-6: clkout and i/o timing table 21-6: clkout and i/o timing requirements param no. symbol characteristic min max units conditions t rc pll start-up time (lock time) ? 2 ms ? clk clkout stability (jitter) using pll -2 +2 % param. no. symbol characteristic min typ max units conditions 10 tosh2ckl osc1 ? to clkout ? ? 75 200 ns (1) 11 tosh2ckh osc1 ? to clkout ? ? 75 200 ns (1) 12 tckr clkout rise time ? 35 100 ns (1) 13 tckf clkout fall time ? 35 100 ns (1) 14 tckl2iov clkout ? to port out valid ? ? 0.5t cy + 20 ns (1) 15 tiov2ckh port in valid before clkout ? 0.25t cy + 25 ? ? ns (1) 16 tckh2ioi port in hold after clkout ? 0??ns (1) 17 tosh2iov osc1 ? (q1 cycle) to port out valid ? 50 150 ns 18 tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) pic18 c xxx 100 ? ? ns 18a pic18 lc xxx 200 ? ? ns 19 tiov2osh port input valid to osc1 ?? (i/o in setup time) 0??ns 20 tior port output rise time pic18 c xxx ? 12 25 ns 20a pic18 lc xxx ? ? 50 ns 21 tiof port output fall time pic18 c xxx ? 12 25 ns 21a pic18 lc xxx ? ? 50 ns 22?? t inp int pin high or low time t cy ??ns 23?? t rbp rb7:rb4 change int high or low time t cy ??ns 24?? t rcp rc7:rc4 change int high or low time 20 ns ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 21-4 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic18cxx2 ds39026d-page 248 ? 1999-2013 microchip technology inc. figure 21-7: reset, watchdog timer, os cillator start-up timer and power-up timer timing figure 21-8: brown-out r eset timing table 21-7: reset, watchdog timer, oscill ator start-up timer, power-up timer and brown-out reset requirements param. no. symbol characteristic min typ max units conditions 30 tmcl mclr pulse width (low) 2 ? ? ? s 31 t wdt watchdog timer time-out period (no postscaler) 71833ms 32 t ost oscillation start-up timer period 1024t osc ? 1024t osc ?t osc = osc1 period 33 t pwrt power up timer period 28 72 132 ms 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset ?2? ? s 35 t bor brown-out reset pulse width 200 ? ? ? sv dd ? b vdd (see d005) 36 tivrst time for internal reference voltage to become stable ?2050 ? s v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 21-4 for load conditions. v dd bv dd 35 v bgap = 1.2v v irvst enable internal reference voltage internal reference voltage stable 36
? 1999-2013 microchip technology inc. ds39026d-page 249 pic18cxx2 figure 21-9: timer0 and timer1 external clock timings table 21-8: timer0 and timer1 external clock requirements note: refer to figure 21-4 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t1cki tmr0 or tmr1 param no. symbol characteristic min max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ? ns with prescaler 10 ? ns 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ? ns with prescaler 10 ? ns 42 tt0p t0cki period no prescaler t cy + 10 ? ns with prescaler greater of: 20 n s or t cy + 40 n ?nsn = prescale value (1, 2, 4,..., 256) 45 tt1h t1cki high time synchronous, no prescaler 0.5t cy + 20 ? ns synchronous, with prescaler pic18 c xxx 10 ? ns pic18 lc xxx 25 ? ns asynchronous pic18 c xxx 30 ? ns pic18 lc xxx 40 ? ns 46 tt1l t1cki low time synchronous, no prescaler 0.5t cy + 20 ? ns synchronous, with prescaler pic18 c xxx 15 ? ns pic18 lc xxx 30 ? ns asynchronous pic18 c xxx 30 ? ns pic18 lc xxx 40 ? ns 47 tt1p t1cki input period synchronous greater of: 20 n s or t cy + 40 n ?nsn = prescale value (1, 2, 4, 8) asynchronous 60 ? ns ft1 t1cki oscillator input frequency range dc 50 khz 48 tcke2tmri delay from external t1cki clock edge to timer increment 2t osc 7t osc ?
pic18cxx2 ds39026d-page 250 ? 1999-2013 microchip technology inc. figure 21-10: capture/compare/pwm timi ngs (ccp1 and ccp2) table 21-9: capture/compare/pwm requirements (ccp1 and ccp2) note: refer to figure 21-4 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) param. no. symbol characteristic min max units conditions 50 tccl ccpx input low time no prescaler 0.5t cy + 20 ? ns with prescaler pic18 c xxx 10 ? ns pic18 lc xxx 20 ? ns 51 tcch ccpx input high time no prescaler 0.5t cy + 20 ? ns with prescaler pic18 c xxx 10 ? ns pic18 lc xxx 20 ? ns 52 tccp ccpx input period 3t cy + 40 n ? ns n = prescale value (1,4 or 16) 53 tccr ccpx output fall time pic18 c xxx ? 25 ns pic18 lc xxx ? 50 ns 54 tccf ccpx output fall time pic18 c xxx ? 25 ns pic18 lc xxx ? 50 ns
? 1999-2013 microchip technology inc. ds39026d-page 251 pic18cxx2 figure 21-11: parallel slave port timing (pic18c4x2) table 21-10: parallel slave port requirements (pic18c4x2) note: refer to figure 21-4 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65 param. no. symbol characteristic min max units conditions 62 tdtv2wrh data in valid before wr ? or cs ? (setup time) 20 25 ? ? ns ns extended temp. range 63 twrh2dti wr ? or cs ? to data?in invalid (hold time) pic18 c xxx 20 ? ns pic18 lc xxx 35 ? ns 64 trdl2dtv rd ? and cs ? to data?out valid ? ? 80 90 ns ns extended temp. range 65 trdh2dti rd ? or cs ? to data?out invalid 10 30 ns 66 tibfinh inhibit of the ibf flag bit being cleared from wr ? or cs ? ?3t cy
pic18cxx2 ds39026d-page 252 ? 1999-2013 microchip technology inc. figure 21-12: example spi master mode timing (cke = 0) table 21-11: example spi mode requirements (master mode, cke = 0) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 note: refer to figure 21-4 for load conditions. param. no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss ? to sck ? or sck ? input t cy ?ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ns (note 2) 74 tsch2dil, ts c l 2 d i l hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 c xxx ? 25 ns pic18 lc xxx ? 45 ns 76 tdof sdo data output fall time ? 25 ns 78 tscr sck output rise time (master mode) pic18 c xxx ? 25 ns pic18 lc xxx ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 c xxx ? 50 ns pic18 lc xxx ? 100 ns note 1: requires the use of parameter # 73a. 2: only if parameter # 71a and # 72a are used.
? 1999-2013 microchip technology inc. ds39026d-page 253 pic18cxx2 figure 21-13: example spi master mode timing (cke = 1) table 21-12: example spi mode requirements (master mode, cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb note: refer to figure 21-4 for load conditions. param. no. symbol characteristic min max units conditions 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ns (note 2) 74 tsch2dil, ts c l 2 d i l hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 c xxx ? 25 ns pic18 lc xxx 45 ns 76 tdof sdo data output fall time ? 25 ns 78 tscr sck output rise time (master mode) pic18 c xxx ? 25 ns pic18 lc xxx 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 c xxx ? 50 ns pic18 lc xxx 100 ns 81 tdov2sch, tdov2scl sdo data output setup to sck edge t cy ?ns note 1: requires the use of parameter # 73a. 2: only if parameter # 71a and # 72a are used.
pic18cxx2 ds39026d-page 254 ? 1999-2013 microchip technology inc. figure 21-14: example spi slave mode timing (cke = 0) table 21-13: example spi mode requirements (slave mode timing (cke = 0)) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 note: refer to figure 21-4 for load conditions. param. no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss ? to sck ? or sck ? input t cy ?ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte1 to the first clock edge of byte2 1.5t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 c xxx ? 25 ns pic18 lc xxx 45 ns 76 tdof sdo data output fall time ? 25 ns 77 tssh2doz ss ? to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic18 c xxx ? 25 ns pic18 lc xxx 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 c xxx ? 50 ns pic18 lc xxx 100 ns 83 tsch2ssh, tscl2ssh ss ? after sck edge 1.5t cy + 40 ? ns note 1: requires the use of parameter # 73a. 2: only if parameter # 71a and # 72a are used.
? 1999-2013 microchip technology inc. ds39026d-page 255 pic18cxx2 figure 21-15: example spi slave mode timing (cke = 1) table 21-14: example spi slave mode requirements (cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 note: refer to figure 21-4 for load conditions. param. no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss ? to sck ? or sck ? input t cy ?ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73a t b 2 b last clock edge of byte1 to the first clock edge of byte2 1.5t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ?ns 75 tdor sdo data output rise time pic18 c xxx ? 25 ns pic18 lc xxx 45 ns 76 tdof sdo data output fall time ? 25 ns 77 tssh2doz ss ? to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic18 c xxx ? 25 ns pic18 lc xxx ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 c xxx ? 50 ns pic18 lc xxx ? 100 ns 82 tssl2dov sdo data output valid after ss ? edge pic18 c xxx ? 50 ns pic18 lc xxx ? 100 ns 83 tsch2ssh, tscl2ssh ss ? after sck edge 1.5t cy + 40 ?ns note 1: requires the use of parameter # 73a. 2: only if parameter # 71a and # 72a are used.
pic18cxx2 ds39026d-page 256 ? 1999-2013 microchip technology inc. figure 21-16: i 2 c bus start/stop bits timing table 21-15: i 2 c bus start/stop bits requirements (slave mode) note: refer to figure 21-4 for load conditions. 91 92 93 scl sda start condition stop condition 90 param. no. symbol characteristic min max units conditions 90 tsu:sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? 91 thd:sta start condition 100 khz mode 4000 ? ns after this period the first clock pulse is generated hold time 400 khz mode 600 ? 92 tsu:sto stop condition 100 khz mode 4700 ? ns setup time 400 khz mode 600 ? 93 thd:sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ?
? 1999-2013 microchip technology inc. ds39026d-page 257 pic18cxx2 figure 21-17: i 2 c bus data timing table 21-16: i 2 c bus data requirements (slave mode) param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? ? s pic18cxxx must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? ? s pic18cxxx must operate at a minimum of 10 mhz ssp module 1.5t cy ? 101 t low clock low time 100 khz mode 4.7 ? ? s pic18cxxx must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? ? s pic18cxxx must operate at a minimum of 10 mhz ssp module 1.5t cy ? 102 t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1c b 300 ns c b is specified to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1c b 300 ns c b is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? ? s only relevant for repeated start condition 400 khz mode 0.6 ? ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? ? s after this period the first clock pulse is generated 400 khz mode 0.6 ? ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ? s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? ? s 400 khz mode 0.6 ? ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110 t buf bus free time 100 khz mode 4.7 ? ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ? s d102 c b bus capacitive loading ? 400 pf note 1: as a transmitter, the device must provide this internal minimu m delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but the requirement t su : dat ? 250 ns must then be met. this will automatically be t he case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. note: refer to figure 21-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic18cxx2 ds39026d-page 258 ? 1999-2013 microchip technology inc. figure 21-18: master ssp i 2 c bus start/stop bits timing waveforms table 21-17: master ssp i 2 c bus start/stop bits requirements note: refer to figure 21-4 for load conditions. 91 93 scl sda start condition stop condition 90 92 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns only relevant for repeated start condition setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 91 t hd : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns after this period the first clock pulse is generated hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 92 t su : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 93 t hd : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? note 1: maximum pin capacitance = 10 pf for all i 2 c pins.
? 1999-2013 microchip technology inc. ds39026d-page 259 pic18cxx2 figure 21-19: master ssp i 2 c bus data timing table 21-18: master ssp i 2 c bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 102 t r sda and scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1c b 300 ns 1 mhz mode (1) ? 300 ns 103 t f sda and scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1c b 300 ns 1 mhz mode (1) ? 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ? ms after this period the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ms 1 mhz mode (1) tbd ? ns 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 1 mhz mode (1) tbd ? ns 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 109 t aa output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode (1) ??ns 110 t buf bus free time 100 khz mode 4.7 ? ms time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ms 1 mhz mode (1) tbd ? ms d102 c b bus capacitive loading ? 400 pf note 1: maximum pin capacitance = 10 pf for all i 2 c pins. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but parameter #107 ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 khz mode) before the scl line is released. note: refer to figure 21-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
pic18cxx2 ds39026d-page 260 ? 1999-2013 microchip technology inc. figure 21-20: usart synchronous transmission (master/slave) timing table 21-19: usart synchronous tran smission requirements figure 21-21: usart synchrono us receive (master/slave) timing table 21-20: usart synchronous rece ive requirements 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin note: refer to figure 21-4 for load conditions. param. no. symbol characteristic min max units conditions 120 tckh2dtv sync xmit (master & slave) clock high to data out valid pic18 c xxx ? 40 ns pic18 lc xxx ? 100 ns 121 tckrf clock out rise time and fall time (master mode) pic18 c xxx ? 25 ns pic18 lc xxx ? 50 ns 122 tdtrf data out rise time and fall time pic18 c xxx ? 25 ns pic18 lc xxx ? 50 ns 125 126 rc6/tx/ck rc7/rx/dt pin pin note: refer to figure 21-4 for load conditions. param. no. symbol characteristic min max units conditions 125 tdtv2ckl sync rcv (master & slave) data hold before ck ? (dt hold time) 10 ? ns 126 tckl2dtl data hold after ck ? (dt hold time) 15 ? ns
? 1999-2013 microchip technology inc. ds39026d-page 261 pic18cxx2 table 21-21: a/d converter characteristics: pic18cxx2 (industrial, extended) pic18lcxx2 (industrial) param no. symbol characteristic min typ max units conditions a01 n r resolution ? ? ? ? 10 10 bit bit v ref = v dd ? 3.0v v ref = v dd ? 3.0v a03 e il integral linearity error ? ? ? ? <1 <2 lsb lsb v ref = v dd ? 3.0v v ref = v dd ? 3.0v a04 e dl differential linearity error ? ? ? ? <1 <2 lsb lsb v ref = v dd ? 3.0v v ref = v dd ? 3.0v a05 e fs full scale error ? ? ? ? <1 <1 lsb lsb v ref = v dd ? 3.0v v ref = v dd ? 3.0v a06 e off offset error ? ? ? ? <1 <1 lsb lsb v ref = v dd ? 3.0v v ref = v dd ? 3.0v a10 ? monotonicity guaranteed (3) ?v ss ? v ain ? v ref a20 v ref reference voltage (v refh - v refl ) 0v ? ? v a20a 3v ? ? v for 10-bit resolution a21 v refh reference voltage high av ss ?av dd + 0.3v v a22 v refl reference voltage low av ss - 0.3v ?av dd v a25 v ain analog input voltage av ss - 0.3v ?v ref + 0.3v v a30 z ain recommended impedance of analog voltage source ??10.0k ? a40 i ad a/d conversion current (v dd ) pic18 c xxx ? 180 ? ? a average current consumption when a/d is on (note 1) . pic18 lc xxx ? 90 ? ? a a50 i ref v ref input current (note 2) 10 ? ? ? 1000 10 ? a ? a during v ain acquisition. based on differential of v hold to v ain . to charge c hold , see section 16.0. during a/d conversion cycle. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. v ref current is from ra2/an2/v ref - and ra3/an3/v ref + pins or av dd and av ss pins, whichever is selected as reference input. 2: v ss ? v ain ? v ref 3: the a/d conversion result never decreases with an increase in the input voltage, and has no missing codes.
pic18cxx2 ds39026d-page 262 ? 1999-2013 microchip technology inc. figure 21-22: a/d conversion timing table 21-22: a/d conversion requirements param no. symbol characteristic min max units conditions 130 t ad a/d clock period pic18 c xxx 1.6 20 (5) ? st osc based, v ref ? 3.0v pic18 lc xxx 3.0 20 (5) ? st osc based, v ref full range pic18 c xxx 2.0 6.0 ? s a/d rc mode pic18 lc xxx 3.0 9.0 ? s a/d rc mode 131 t cnv conversion time (not including acquisition time) (note 1) 11 12 t ad 132 t acq acquisition time (note 3) 15 10 ? ? ? s ? s -40 ? c ? te mp ? 125 ? c 0 ? c ? tem p ? 125 ? c 135 t swc switching time from convert ? sample ? (note 4) 136 t amp amplifier settling time (note 2) 1? ? s this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 5 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). note 1: adres register may be read on the following t cy cycle. 2: see section 16.0 for minimum conditions, when input voltage has changed more than 1 lsb. 3: the time for the holding capacitor to acquire the ?new? input voltage, when the voltage changes full scale after the conversion (av dd to av ss , or av ss to av dd ). the source impedance ( r s ) on the input channels is 50 ? . 4: on the next q4 cycle of the device clock. 5: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data note 2 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy
? 1999-2013 microchip technology inc. ds39026d-page 263 pic18cxx2 22.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested . the data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'typical' represents the mean of the distribution at 25 ? c. 'max' or 'min' represents (mean + 3 ? ) or (mean - 3 ? ) respectively, where ? is standard deviation, over the whole temperature range. figure 22-1: typical i dd vs. f osc over v dd (hs mode) figure 22-2: maximum i dd vs. f osc over v dd (hs mode) 0 2 4 6 8 10 12 14 16 4 6 8 101214161820222426 f osc (m hz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.7v 3.2v typical: statistical mean @ 25c maximum: mean + 3s (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0 2 4 6 8 10 12 14 16 4 6 8 101214161820222426 f osc (m hz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 3.2v 2.7v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
pic18cxx2 ds39026d-page 264 ? 1999-2013 microchip technology inc. figure 22-3: typical i dd vs. f osc over v dd (hs/pll mode) figure 22-4: maximum i dd vs. f osc over v dd (hs/pll mode) 0 5 10 15 20 25 45678910 f osc (mhz) i dd (ma) 5.0v 5.5v 4.5v 4.0v 3.5v 3.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0 5 10 15 20 25 45678910 f osc (mhz) i dd (ma) 5.0v 5.5v 4.5v 4.0v 3.5v 3.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
? 1999-2013 microchip technology inc. ds39026d-page 265 pic18cxx2 figure 22-5: typical i dd vs. f osc over v dd (xt mode) figure 22-6: maximum i dd vs. f osc over v dd (xt mode) 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
pic18cxx2 ds39026d-page 266 ? 1999-2013 microchip technology inc. figure 22-7: typical i dd vs. f osc over v dd (lp mode) figure 22-8: maximum i dd vs. f osc over v dd (lp mode) 0 20 40 60 80 100 120 140 160 180 200 20 30 40 50 60 70 80 90 100 f osc (khz) i dd (ua) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0 50 100 150 200 250 300 20 30 40 50 60 70 80 90 100 f osc (khz) i dd (ua) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
? 1999-2013 microchip technology inc. ds39026d-page 267 pic18cxx2 figure 22-9: typical and maximum i dd vs. v dd (timer1 as main oscillator, 32.768 khz, c = 47 pf) figure 22-10: average f osc vs. v dd for various values of r (rc mode, c = 20 pf, 25 ? c) 0 50 100 150 200 250 300 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd (ua) max (-40c) typ (25c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.53.03.54.04.55.05.5 v dd (v) freq (mhz) 3.3k ? 5.1k ? 10k ? 100k ?
pic18cxx2 ds39026d-page 268 ? 1999-2013 microchip technology inc. figure 22-11: average f osc vs. v dd for various values of r (rc mode, c = 100 pf, 25 ? c) figure 22-12: average f osc vs. v dd for various values of r (rc mode, c = 300 pf, 25 ? c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (mhz) 3.3k ? 5.1k ? 10k ? 100k ? 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.53.03.54.04.55.05.5 v dd (v) freq (mhz) 3.3k ? 5.1k ? 10k ? 100k ?
? 1999-2013 microchip technology inc. ds39026d-page 269 pic18cxx2 figure 22-13: i pd vs. v dd (sleep mode, all peripherals disabled) figure 22-14: ? i bor vs. v dd over temperature (bor enabled, v bor = 2.50v - 2.66v) 0.01 0.10 1.00 10.00 100.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) max (125c) max (85c) typ (25c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0 25 50 75 100 125 150 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) ? i bor ( ? a) max ? i bor (-40c to 125c) ty p ? i bor (25c) indeterminate state (may be in reset or sleep device in sleep maximum reset current - example only (depends on osc mode, osc freq, temp, v dd ) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
pic18cxx2 ds39026d-page 270 ? 1999-2013 microchip technology inc. figure 22-15: typical and maximum ?? i tmr1 vs. v dd over temperature (-40 ? c to +125 ? c, timer1 with oscillator, xtal=32 khz, c1 and c2 = 47 pf) figure 22-16: typical and maximum ? i wdt vs. v dd over temperature (wdt enabled) 0 10 20 30 40 50 60 70 80 90 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) ? i tmr1osc ( ? a) max (-40c to 125c) typ (25c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) ? i wdt ( ? a) maximum (-40c) typical (25c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
? 1999-2013 microchip technology inc. ds39026d-page 271 pic18cxx2 figure 22-17: typical, minimum and maximum wdt period vs. v dd (-40 ? c to +125 ? c) figure 22-18: ? i lvd vs. v dd over temperature (lvd enabled, v lvd = 3.0v - 3.2v) 0 10 20 30 40 50 60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) wdt period (ms) max (125c) min (-40c) ty p (25c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0 5 10 15 20 25 30 35 40 45 50 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) ? i lvd ( ? a) typ (25c) max (-40c to 125c) typ (25c) lvdif is set by hardware lvdif can be cleared by firmware lvdif is unknown max (-40c to 125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
pic18cxx2 ds39026d-page 272 ? 1999-2013 microchip technology inc. figure 22-19: ? i lvd vs. v dd over temperature (lvd enabled, v lvd = 4.5v - 4.78v) figure 22-20: typical, minimum and maximum v oh vs. i oh (v dd = 5v, -40 ? c to +125 ? c) 0 5 10 15 20 25 30 35 40 45 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) ? i lvd ( ? a) ty p (25c) max (125c) typ (25c) lvdif is set by hardware lvdif can be cleared by firmware lvdif is unknown max (125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 5 10 15 20 25 i oh (-ma) v oh (v) max (-40c) ty p (25c) min (125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
? 1999-2013 microchip technology inc. ds39026d-page 273 pic18cxx2 figure 22-21: typical, minimum and maximum v oh vs. i oh (v dd = 3v, -40 ? c to +125 ? c) figure 22-22: typical and maximum v ol vs. i ol (v dd = 5v, -40 ? c to +125 ? c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 i oh (-ma) v oh (v) max (-40c) typ (25c) min (125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 5 10 15 20 25 i ol (ma) v ol (v) max (-40c to 125c) ty p (25c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
pic18cxx2 ds39026d-page 274 ? 1999-2013 microchip technology inc. figure 22-23: typical and maximum v ol vs. i ol (v dd = 3v, -40 ? c to +125 ? c) figure 22-24: minimum and maximum v in vs. v dd (st input, -40 ? c to +125 ? c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0 5 10 15 20 25 i ol (ma) v ol (v) max (-40c to 125c) ty p (25c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max (125c) v ih min (-40c) v il max (-40c) v il min (125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
? 1999-2013 microchip technology inc. ds39026d-page 275 pic18cxx2 figure 22-25: minimum and maximum v in vs. v dd , (ttl input, -40 ? c to +125 ? c) figure 22-26: minimum and maximum v in vs. v dd (i 2 c input, -40 ? c to +125 ? c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) max v th (-40c) min v th (125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) max v ih (125c) min v ih (-40c) min v il (-40c) max v il (125c) typical: statistical mean @ 25c maximum: mean + 3 ? (-40c to 125c) minimum: mean ? 3 ? (-40c to 125c)
pic18cxx2 ds39026d-page 276 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 277 pic18cxx2 23.0 packaging information 23.1 package marking information 28-lead soic yywwnnn example xxxxxxxxxxxxxxxxx yywwnnn 28-lead pdip (skinny dip) example xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx 0117017 PIC18C242-i/sp xxxxxxxxxxxxxxxxxxxx 0110017 PIC18C242-e/so legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
pic18cxx2 ds39026d-page 278 ? 1999-2013 microchip technology inc. package marking information (cont?d) 44-lead tqfp example 44-lead plcc example xxxxxxxxxx xxxxxxxxxx 28- and 40-lead jw (cerdip) example xxxxxxxxxxxxxxxxxx 40-lead pdip example xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx yywwnnn pic18c442-i/p 0112017 xxxxxxxxxxx xxxxxxxxxxx xxxxxxxxxxx yywwnnn pic18c452 -i/jw 0115017 xxxxxxxxxx xxxxxxxxxx yywwnnn pic18c442 -e/pt 0120017 xxxxxxxxxx xxxxxxxxxx yywwnnn pic18c452 -i/l 0120017
? 1999-2013 microchip technology inc. ds39026d-page 279 pic18cxx2 23.2 package details the following sections give the technical details of the packages. 28-lead skinny plastic dual in -line (sp) ? 300 mil (pdip) 15 10 5 15 10 5 ? mold draft angle bottom 15 10 5 15 10 5 ? mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb ? e ? p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic18cxx2 ds39026d-page 280 ? 1999-2013 microchip technology inc. 28-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle top ? 048048 15 12 0 15 12 0 ? mold draft angle bottom 15 12 0 15 12 0 ? mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c ? 45 ? h ? a2 ? a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1999-2013 microchip technology inc. ds39026d-page 281 pic18cxx2 40-lead plastic dual in-line (p) ? 600 mil (pdip) 15 10 5 15 10 5 ? mold draft angle bottom 15 10 5 15 10 5 ? mold draft angle top 17.27 16.51 15.75 .680 .650 .620 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.27 0.76 .070 .050 .030 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.05 .135 .130 .120 l tip to seating plane 52.45 52.26 51.94 2.065 2.058 2.045 d overall length 14.22 13.84 13.46 .560 .545 .530 e1 molded package width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 4.06 3.81 3.56 .160 .150 .140 a2 molded package thickness 4.83 4.45 4.06 .190 .175 .160 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 1 2 d n e1 c ? eb e ? p l b b1 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-011 drawing no. c04-016 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic18cxx2 ds39026d-page 282 ? 1999-2013 microchip technology inc. 28-lead ceramic dual in-line with window (jw) ? 600 mil (cerdip) 7.37 7.11 6.86 .290 .280 .270 w window diameter 18.03 16.76 15.49 .710 .660 .610 eb overall row spacing 0.58 0.51 0.41 .023 .020 .016 b lower lead width 1.65 1.46 1.27 .065 .058 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.81 3.49 3.18 .150 .138 .125 l tip to seating plane 37.85 37.08 36.32 1.490 1.460 1.430 d overall length 13.36 13.21 13.06 .526 .520 .514 e1 ceramic pkg. width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 1.52 0.95 0.38 .060 .038 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 5.72 5.33 4.95 .225 .210 .195 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 w c e eb p a2 l b1 b a1 a * controlling parameter significant characteristic jedec equivalent: mo-103 drawing no. c04-013 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1999-2013 microchip technology inc. ds39026d-page 283 pic18cxx2 40-lead ceramic dual in-line with window (jw) ? 600 mil (cerdip) 9.14 8.89 8.64 .360 .350 .340 w window diameter 18.03 16.76 15.49 .710 .660 .610 eb overall row spacing 0.58 0.51 0.41 .023 .020 .016 b lower lead width 1.40 1.33 1.27 .055 .053 .050 b1 upper lead width 0.36 0.28 0.20 .014 .011 .008 c lead thickness 3.68 3.56 3.43 .145 .140 .135 l tip to seating plane 52.32 52.07 51.82 2.060 2.050 2.040 d overall length 13.36 13.21 13.06 .526 .520 .514 e1 ceramic pkg. width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 1.52 1.14 0.76 .060 .045 .030 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 5.72 5.21 4.70 .225 .205 .185 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n c eb e p b1 b * controlling parameter significant characteristic jedec equivalent: mo-103 drawing no. c04-014 e1 w a2 a a1 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic18cxx2 ds39026d-page 284 ? 1999-2013 microchip technology inc. 44-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-076 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) a a1 a2 ? e e1 #leads=n1 p b d1 d n 1 2 ? c ? l units inches millimeters* dimension limits min nom max min nom max number of pins n 44 44 pitch p .031 0.80 overall height a .039 .043 .047 1.00 1.10 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle ? 03.5 7 03.5 7 overall width e .463 .472 .482 11.75 12.00 12.25 overall length d .463 .472 .482 11.75 12.00 12.25 molded package width e1 .390 .394 .398 9.90 10.00 10.10 molded package length d1 .390 .394 .398 9.90 10.00 10.10 pins per side n1 11 11 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .012 .015 .017 0.30 0.38 0.44 mold draft angle top ? 51015 51015 mold draft angle bottom ? 51015 51015 ch x 45 ? significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 1999-2013 microchip technology inc. ds39026d-page 285 pic18cxx2 44-lead plastic leaded chip carrier (l) ? square (plcc) ch2 x 45 ? ch1 x 45 ? 10 5 0 10 5 0 ? mold draft angle bottom 10 5 0 10 5 0 ? mold draft angle top 0.53 0.51 0.33 .021 .020 .013 b 0.81 0.74 0.66 .032 .029 .026 b1 upper lead width 0.33 0.27 0.20 .013 .011 .008 c lead thickness 11 11 n1 pins per side 16.00 15.75 14.99 .630 .620 .590 d2 footprint length 16.00 15.75 14.99 .630 .620 .590 e2 footprint width 16.66 16.59 16.51 .656 .653 .650 d1 molded package length 16.66 16.59 16.51 .656 .653 .650 e1 molded package width 17.65 17.53 17.40 .695 .690 .685 d overall length 17.65 17.53 17.40 .695 .690 .685 e overall width 0.25 0.13 0.00 .010 .005 .000 ch2 corner chamfer (others) 1.27 1.14 1.02 .050 .045 .040 ch1 corner chamfer 1 0.86 0.74 0.61 .034 .029 .024 a3 side 1 chamfer height 0.51 .020 a1 standoff a2 molded package thickness 4.57 4.39 4.19 .180 .173 .165 a overall height 1.27 .050 p pitch 44 44 n number of pins max nom min max nom min dimension limits millimeters inches* units ? a2 c e2 2 d d1 n #leads=n1 e e1 1 ? p a3 a 35 ? b1 b d2 a1 .145 .153 .160 3.68 3.87 4.06 .028 .035 0.71 0.89 lower lead width * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-047 drawing no. c04-048 significant characteristic note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic18cxx2 ds39026d-page 286 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 287 pic18cxx2 appendix a: revision history revision a (july 1999) original data sheet for pic18cxx2 family. revision b (march 2001) added dc and ac characteristics graphs (section 22.0). revision c (january 2013) added a note to each package outline drawing. appendix b: device differences the differences between the devices listed in this data sheet are shown in table 1. table 1: device differences feature PIC18C242 pic18c252 pic18c442 pic18c452 program memory (kbytes) 16 32 16 32 data memory (bytes) 512 1536 512 1536 a/d channels 5 5 8 8 parallel slave port (psp) no no yes yes package types 28-pin dip 28-pin soic 28-pin jw 28-pin dip 28-pin soic 28-pin jw 40-pin dip 44-pin plcc 44-pin tqfp 40-pin jw 40-pin dip 44-pin plcc 44-pin tqfp 40-pin jw
pic18cxx2 ds39026d-page 288 ? 1999-2013 microchip technology inc. appendix c: conversion considerations this appendix discusses the considerations for con- verting from previous versions of a device to the ones listed in this data sheet. typically, these changes are due to the differences in the process technology used. an example of this type of conversion is from a pic16c74a to a pic16c74b. not applicable appendix d: migration from baseline to enhanced devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to an enhanced mcu device (i.e., pic18cxxx). the following are the list of modifications over the pic16c5x microcontroller family: not currently available
? 1999-2013 microchip technology inc. ds39026d-page 289 pic18cxx2 appendix e: migration from mid-range to enhanced devices a detailed discussion of the differences between the mid-range mcu devices (i.e., pic16cxxx) and the enhanced devices (i.e., pic18cxxx) is provided in an716, ? migrating designs from pic16c74a/74b to pic18c442 .? the changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. this application note is available as literature number ds00716. appendix f: migration from high-end to enhanced devices a detailed discussion of the migration pathway and dif- ferences between the high-end mcu devices (i.e., pic17cxxx) and the enhanced devices (i.e., pic18cxxx) is provided in an726, ? pic17cxxx to pic18cxxx migration .? this application note is avail- able as literature number ds00726.
pic18cxx2 ds39026d-page 290 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 291 pic18cxx2 index a a/d ................................................................................... 165 a/d converter flag (adif bit) ................................. 167 a/d converter interrupt, configuring ....................... 168 adcon0 register .................................................... 165 adcon1 register ............................................ 165, 166 adres register .............................................. 165, 167 analog port pins .................................................. 89, 90 analog port pins, configuring .................................. 170 associated registers ............................................... 172 block diagram .......................................................... 167 block diagram, analog input model ......................... 168 configuring the module ............................................ 168 conversion clock (t ad ) ........................................... 170 conversion status (go/done bit) .......................... 167 conversions ............................................................. 171 converter characteristics ........................................ 261 equations ................................................................. 169 sampling requirements ........................................... 168 sampling time ......................................................... 169 special event trigger (ccp) ............................ 110, 171 timing diagram ........................................................ 262 absolute maximum ratings ............................................. 235 ackstat ........................................................................ 139 adcon0 register ............................................................ 165 go/done bit ........................................................... 167 adcon1 register .................................................... 165, 166 addlw ............................................................................ 193 addwf ............................................................................ 193 addwfc ......................................................................... 194 adres register ...................................................... 165, 167 analog-to-digital converter. see a/d andlw ............................................................................ 194 andwf ............................................................................ 195 assembler mpasm assembler .................................................. 229 b baud rate generator ....................................................... 136 bc .................................................................................... 195 bcf .................................................................................. 196 bf .................................................................................... 139 block diagrams a/d converter .......................................................... 167 analog input model .................................................. 168 baud rate generator ............................................... 136 capture mode operation ......................................... 109 compare mode operation ....................................... 110 low voltage detect external reference source .............................. 174 internal reference source ............................... 174 mssp i 2 c mode .......................................................... 128 spi mode ......................................................... 121 on-chip reset circuit ................................................ 25 parallel slave port (portd and porte) ................. 90 porta ra3:ra0 and ra5 port pins ............................. 77 ra4/t0cki pin .................................................. 78 ra6 pin .............................................................. 78 portb rb3 pin ............................................................. 81 rb3:rb0 port pins ............................................ 81 rb7:rb4 port pins ............................................ 80 portc (peripheral output override) ........................ 83 portd (i/o mode) .................................................... 85 porte (i/o mode) .................................................... 87 pwm operation (simplified) .................................... 112 ssp (spi mode) ...................................................... 121 timer1 ....................................................................... 98 timer1 (16-bit r/w mode) ......................................... 98 timer2 ..................................................................... 102 timer3 ..................................................................... 104 timer3 (16-bit r/w mode) ....................................... 104 usart asynchronous receive .................................... 157 asynchronous transmit ................................... 155 watchdog timer ...................................................... 184 bn .................................................................................... 196 bnc ................................................................................. 197 bnov .............................................................................. 198 bnz ................................................................................. 198 bor. see brown-out reset bov ................................................................................. 201 bra ................................................................................. 199 brg. see baud rate generator brown-out reset (bor) ............................................. 26, 179 timing diagram ....................................................... 248 bsf .................................................................................. 199 btfsc ............................................................................. 200 btfss ............................................................................. 200 btg ................................................................................. 201 bus collision during a repeated start condition ........ 147 bus collision during a start condition ........................ 145 bus collision during a stop condition .......................... 148 bz .................................................................................... 202 c call ................................................................................ 202 capture (ccp module) .................................................... 109 associated registers ............................................... 111 block diagram ......................................................... 109 ccp pin configuration ............................................ 109 ccpr1h:ccpr1l registers .................................. 109 software interrupt .................................................... 109 timer1 mode selection ............................................ 109 capture/compare/pwm (ccp) ....................................... 107 capture mode. see capture ccp1 ....................................................................... 108 ccpr1h register ........................................... 108 ccpr1l register ............................................ 108 ccp1con and ccp2con registers ..................... 107 ccp2 ....................................................................... 108 ccpr2h register ........................................... 108 ccpr2l register ............................................ 108 compare mode. see compare interaction of two ccp modules ............................. 108 pwm mode. see pwm timer resources ..................................................... 108 timing diagram ....................................................... 250 clocking scheme ............................................................... 39 clrf ............................................................................... 203 clrwdt ......................................................................... 203
pic18cxx2 ds39026d-page 292 ? 1999-2013 microchip technology inc. code examples 16 x 16 signed multiply routine ................................ 62 16 x 16 unsigned multiply routine ............................ 62 8 x 8 signed multiply routine .................................... 61 8 x 8 unsigned multiply routine ................................ 61 changing between capture prescalers ................... 109 fast register stack .................................................... 39 initializing porta ...................................................... 77 initializing portb ...................................................... 80 initializing portc ...................................................... 83 initializing portd ...................................................... 85 initializing porte ...................................................... 87 loading the sspbuf register ................................ 122 saving status, wreg and bsr registers in ram ............................................................... 75 code protection ....................................................... 179, 186 comf ............................................................................... 204 compare (ccp module) ................................................... 110 associated registers ............................................... 111 block diagram .......................................................... 110 ccp pin configuration ............................................. 110 ccpr1h:ccpr1l registers ................................... 110 software interrupt .................................................... 110 special event trigger ......................... 99, 105, 110, 171 timer1 mode selection ............................................ 110 configuration bits ............................................................. 179 context saving during interrupts ....................................... 75 example code ........................................................... 75 conversion considerations .............................................. 288 cpfseq .......................................................................... 204 cpfsgt ........................................................................... 205 cpfslt ........................................................................... 205 d data memory ...................................................................... 42 general purpose registers ........................................ 42 special function registers ........................................ 42 daw ................................................................................. 206 dc characteristics ................................................... 237, 240 decf ............................................................................... 206 decfsnz ........................................................................ 207 decfsz ........................................................................... 207 device differences ........................................................... 287 direct addressing ............................................................... 51 e electrical characteristics .................................................. 235 errata ................................................................................... 5 f firmware instructions ....................................................... 187 g general call address sequence ...................................... 133 general call address support ......................................... 133 goto ............................................................................... 208 i i/o ports ............................................................................. 77 i 2 c (ssp module) ............................................................ 128 ack pulse ....................................................... 128, 129 addressing ............................................................... 129 block diagram ......................................................... 128 read/write bit information (r/w bit) ....................... 129 reception ................................................................ 129 serial clock (rc3/sck/scl) ................................... 129 slave mode .............................................................. 128 timing diagram, data .............................................. 257 timing diagram, start/stop bits ........................ 256 transmission ........................................................... 129 i 2 c master mode reception ............................................ 139 i 2 c master mode repeated start condition ................ 138 i 2 c module acknowledge sequence timing .............................. 142 baud rate generator block diagram baud rate generator ...................................... 136 brg reset due to sda collision ............................ 146 brg timing ............................................................. 136 bus collision acknowledge ................................................... 144 repeated start condition ............................ 147 repeated start condition timing (case 1) ................................................... 147 repeated start condition timing (case 2) ................................................... 147 start condition ............................................. 145 start condition timing ......................... 145, 146 stop condition ............................................... 148 stop condition timing (case 1) .................... 148 stop condition timing (case 2) .................... 148 transmit timing ............................................... 144 bus collision timing ................................................ 144 clock arbitration ...................................................... 143 clock arbitration timing (master transmit) ............. 143 general call address support ................................. 133 master mode 7-bit reception timing ....................... 141 master mode operation ........................................... 135 master mode start condition ............................... 137 master mode transmission ..................................... 139 master mode transmit sequence ............................ 135 multi-master mode ................................................... 144 repeat start condition timing ............................ 138 stop condition receive or transmit timing .......... 143 stop condition timing ........................................... 142 waveforms for 7-bit reception ................................ 130 waveforms for 7-bit transmission ........................... 130 icepic in-circuit emulator .............................................. 230 id locations ............................................................. 179, 186 incf ................................................................................ 208 incfsz ............................................................................ 209 in-circuit serial programming (icsp) ...................... 179, 186 indirect addressing ............................................................ 51 fsr register ............................................................. 50 infsnz ............................................................................ 209 instruction cycle ................................................................ 39 instruction flow/pipelining ................................................. 40 instruction format ............................................................ 189
? 1999-2013 microchip technology inc. ds39026d-page 293 pic18cxx2 instruction set .................................................................. 187 addlw .................................................................... 193 addwf .................................................................... 193 addwfc ................................................................. 194 andlw .................................................................... 194 andwf .................................................................... 195 bc ............................................................................ 195 bcf .......................................................................... 196 bn ............................................................................ 196 bnc ......................................................................... 197 bnov ....................................................................... 198 bnz .......................................................................... 198 bov ......................................................................... 201 bra .......................................................................... 199 bsf .......................................................................... 199 btfsc ..................................................................... 200 btfss ..................................................................... 200 btg .......................................................................... 201 bz ............................................................................ 202 call ........................................................................ 202 clrf ........................................................................ 203 clrwdt .................................................................. 203 comf ...................................................................... 204 cpfseq .................................................................. 204 cpfsgt .................................................................. 205 cpfslt ................................................................... 205 daw ......................................................................... 206 decf ....................................................................... 206 decfsnz ................................................................ 207 decfsz ................................................................... 207 goto ...................................................................... 208 incf ......................................................................... 208 incfsz .................................................................... 209 infsnz .................................................................... 209 iorlw ..................................................................... 210 iorwf ..................................................................... 210 lfsr ........................................................................ 211 movf ....................................................................... 211 movff .................................................................... 212 movlb .................................................................... 212 movlw ................................................................... 213 movwf ................................................................... 213 mullw .................................................................... 214 mulwf .................................................................... 214 negf ....................................................................... 215 nop ......................................................................... 215 rcall ..................................................................... 217 reset ..................................................................... 217 retfie .................................................................... 218 retlw .................................................................... 218 return .................................................................. 219 rlcf ........................................................................ 219 rlncf ..................................................................... 220 rrcf ....................................................................... 220 rrncf ................................ .................................... 221 setf ........................................................................ 221 sleep ..................................................................... 222 subfwb .................................................................. 222 sublw .................................................................... 223 subwf .................................................................... 223 subwfb .................................................................. 224 swapf .................................................................... 224 tblrd ..................................................................... 225 tblwt ..................................................................... 226 tstfsz ................................................................... 227 xorlw ................................................................... 227 xorwf ................................................................... 228 summary table ....................................................... 190 int interrupt (rb0/int). see interrupt sources intcon register rbif bit ..................................................................... 80 intcon registers ............................................................. 65 inter-integrated circuit. see i 2 c internal program memory read/writes ............................................................... 57 interrupt sources ....................................................... 63, 179 a/d conversion complete ....................................... 168 capture complete (ccp) ........................................ 109 compare complete (ccp) ...................................... 110 int0 ........................................................................... 75 interrupt-on-change (rb7:rb4 ) ............................... 80 portb, on change ................................................... 75 rb0/int pin, external ............................................... 75 ssp receive/transmit complete ............................ 115 tmr0 ......................................................................... 75 tmr0 overflow .......................................................... 95 tmr1 overflow .................................... 97, 99, 103, 105 tmr2 to pr2 match ................................................ 102 tmr2 to pr2 match (pwm) ............................ 101, 112 usart receive/transmit complete ....................... 149 interrupts, enable bits ccp1 enable (ccp1ie bit) ..................................... 109 interrupts, flag bits a/d converter flag (adif bit) ................................. 167 ccp1 flag (ccp1if bit) .................................. 109, 110 interrupt-on-change (rb7:rb4) flag (rbif bit) ....... 80 iorlw ............................................................................. 210 iorwf ............................................................................. 210 ipr registers ..................................................................... 72 k k ee l oq evaluation and programming tools ................... 232 l lfsr ............................................................................... 211 long write and interrupts ............................................................ 59 operation ................................................................... 58 sequence of events .................................................. 58 unexpected termination ........................................... 59 low voltage detect ......................................................... 173 block diagrams external reference source ............................. 174 internal reference source ............................... 174 converter characteristics ........................................ 242 effects of a reset .................................................. 177 operation ................................................................. 176 current consumption ...................................... 177 during sleep ................................................. 177 reference voltage set point ........................... 177 lvd. see low voltage detect.
pic18cxx2 ds39026d-page 294 ? 1999-2013 microchip technology inc. m master synchronous serial port (mssp). see ssp. memory organization data memory ............................................................. 42 program memory ....................................................... 35 migration from baseline to enhanced devices ................ 288 movf ............................................................................... 211 movff ............................................................................. 212 movlb ............................................................................. 212 movlw ............................................................................ 213 movwf ........................................................................... 213 mplab c17 and mplab c18 c compilers ..................... 229 mplab icd in-circuit debugger ...................................... 231 mplab ice high performance universal in-circuit emulator with mplab ide ........................ 230 mplab integrated development environment software .............................................. 229 mplink object linker/mplib object librarian ............... 230 mullw ............................................................................ 214 multi-master mode ........................................................... 144 mulwf ............................................................................ 214 n negf ............................................................................... 215 nop ................................................................................. 215 o on-chip reset circuit block diagram ............................................................ 25 opcode field descriptions ............................................ 188 option_reg register ps2:ps0 bits ............................................................. 95 psa bit ....................................................................... 95 t0cs bit ..................................................................... 95 t0se bit ..................................................................... 95 oscillator configuration .................................................... 179 oscillator configurations .................................................... 17 hs .............................................................................. 17 hs + pll .................................................................... 17 lp ............................................................................... 17 rc ........................................................................ 17, 18 rcio .......................................................................... 17 xt .............................................................................. 17 oscillator, timer1 ......................................... 97, 99, 103, 105 oscillator, wdt ................................................................ 183 p packaging ........................................................................ 277 parallel slave port (psp) ............................................. 85, 90 associated registers ................................................. 91 block diagram ............................................................ 90 re0/rd /an5 pin .................................................. 89, 90 re1/wr /an6 pin ................................................. 89, 90 re2/cs /an7 pin .................................................. 89, 90 read waveforms ....................................................... 91 select (pspmode bit) ........................................ 85, 90 timing diagram ........................................................ 251 write waveforms ....................................................... 90 picdem 1 low cost pic mcu demonstration board ............................................... 231 picdem 17 demonstration board ................................... 232 picdem 2 low cost pic16cxx demonstration board ............................................... 231 picdem 3 low cost pic16cxxx demonstration board ............................................... 232 picstart plus entry level development system ......... 231 pie registers ..................................................................... 70 pin functions mclr /v pp ........................................................... 10, 13 osc1/clkin ....................................................... 10, 13 osc2/clkout ................................................... 10, 13 ra0/an0 .............................................................. 10, 13 ra1/an1 .............................................................. 10, 13 ra2/an2 .............................................................. 10, 13 ra3/an3/v ref ..................................................... 10, 13 ra4/t0cki .......................................................... 10, 13 ra5/an4/ss ........................................................ 10, 13 rb0/int ............................................................... 11, 14 rb1 ...................................................................... 11, 14 rb2 ...................................................................... 11, 14 rb3 ...................................................................... 11, 14 rb4 ...................................................................... 11, 14 rb5 ...................................................................... 11, 14 rb6 ...................................................................... 11, 14 rb7 ...................................................................... 11, 14 rc0/t1oso/t1cki ............................................. 12, 15 rc1/t1osi/ccp2 ................................................ 12, 15 rc2/ccp1 ........................................................... 12, 15 rc3/sck/scl ..................................................... 12, 15 rc4/sdi/sda ...................................................... 12, 15 rc5/sdo ............................................................. 12, 15 rc6/tx/ck .......................................................... 12, 15 rc7/rx/dt .......................................................... 12, 15 rd0/psp0 ................................................................. 16 rd1/psp1 ................................................................. 16 rd2/psp2 ................................................................. 16 rd3/psp3 ................................................................. 16 rd4/psp4 ................................................................. 16 rd5/psp5 ................................................................. 16 rd6/psp6 ................................................................. 16 rd7/psp7 ................................................................. 16 re0/rd /an5 .............................................................. 16 re1/wr /an6 ............................................................. 16 re2/cs /an7 .............................................................. 16 v dd ...................................................................... 12, 16 v ss ...................................................................... 12, 16 pir registers ..................................................................... 68 pointer, fsr ...................................................................... 50 por. see power-on reset. porta associated registers ................................................. 79 initialization ................................................................ 77 porta register ........................................................ 77 ra3:ra0 and ra5 port pins ..................................... 77 ra4/t0cki pin .......................................................... 78 ra6 pin ..................................................................... 78 trisa register .......................................................... 77 portb associated registers ................................................. 82 initialization ................................................................ 80 portb register ........................................................ 80 rb0/int pin, external ................................................ 75 rb3 pin ..................................................................... 81 rb3:rb0 port pins .................................................... 81 rb7:rb4 interrupt-on-change flag (rbif bit) .......... 80 rb7:rb4 port pins .................................................... 80 trisb register .......................................................... 80
? 1999-2013 microchip technology inc. ds39026d-page 295 pic18cxx2 portc associated registers ................................................. 84 block diagram (peripheral output override) ............. 83 initialization .......................................................... 83, 85 portc register ........................................................ 83 rc3/sck/scl pin ................................................... 129 rc7/rx/dt pin ........................................................ 151 trisc register .................................................. 83, 149 portd .............................................................................. 90 associated registers ................................................. 86 block diagram (i/o mode) ......................................... 85 parallel slave port (psp) function ............................ 85 portd register ........................................................ 85 trisd register .......................................................... 85 porte analog port pins .................................................. 89, 90 associated registers ................................................. 89 block diagram (i/o mode) ......................................... 87 initialization ................................................................ 87 porte register ........................................................ 87 psp mode select (pspmode bit) ...................... 85, 90 re0/rd /an5 pin .................................................. 89, 90 re1/wr /an6 pin ................................................. 89, 90 re2/cs /an7 pin .................................................. 89, 90 trise register .................................................... 87, 88 postscaler, wdt assignment (psa bit) ................................................ 95 rate select (ps2:ps0 bits) ....................................... 95 switching between timer0 and wdt ........................ 95 power-down mode. see sleep. power-on reset (por) .............................................. 26, 179 oscillator start-up timer (ost) ......................... 26, 179 power-up timer (pwrt) ................................... 26, 179 time-out sequence .................................................... 26 time-out sequence on power-up ........................ 32, 33 timing diagram ........................................................ 248 prescaler, capture ........................................................... 109 prescaler, timer0 ............................................................... 95 assignment (psa bit) ................................................ 95 rate select (ps2:ps0 bits) ....................................... 95 switching between timer0 and wdt ........................ 95 prescaler, timer1 ............................................................... 98 prescaler, timer2 ............................................................. 112 pro mate ii universal programmer .............................. 231 product identification system .......................................... 301 program counter pcl register .............................................................. 39 pclath register ...................................................... 39 program memory ............................................................... 35 interrupt vector .......................................................... 35 reset vector ............................................................ 35 program verification ........................................................ 186 programming, device instructions ................................... 187 psp. see parallel slave port. pulse width modulation. see pwm (ccp module). pwm (ccp module) ........................................................ 112 associated registers ............................................... 113 block diagram .......................................................... 112 ccpr1h:ccpr1l registers ................................... 112 duty cycle ................................................................ 112 example frequencies/resolutions .......................... 113 output diagram ........................................................ 112 period ....................................................................... 112 setup for pwm operation ........................................ 113 tmr2 to pr2 match ........................................ 101, 112 q q clock ............................................................................ 112 r ram. see data memory. rcall ............................................................................. 217 rcon register ............................................................ 53, 56 rcsta register spen bit .................................................................. 149 register file ....................................................................... 42 registers adcon0 (a/d control 0) ......................................... 165 adcon1 (a/d control 1) ......................................... 166 ccp1con and ccp2con (capture/compare/pwm control) ................... 107 config1h (configuration 1 high) .......................... 180 config1l (configuration 1 low) ........................... 180 config2h (configuration 2 high) .......................... 181 config2l (configuration 2 low) ........................... 181 config3h (configuration 3 high) .......................... 182 config4l (configuration 4 low) ........................... 182 flag ...................................................................... 68, 69 intcon (interrupt control) ....................................... 65 intcon2 (interrupt control 2) .................................. 66 intcon3 (interrupt control 3) .................................. 67 ipr1 (peripheral interrupt priority 1) ......................... 72 ipr2 (peripheral interrupt priority 2) ......................... 73 lvdcon (lvd control) ........................................... 175 pie2 (peripheral interrupt enable 1) ......................... 70 pie2 (peripheral interrupt enable 2) ......................... 71 pir1 (peripheral interrupt request 1) ....................... 68 pir2 (peripheral interrupt request 2) ....................... 69 rcon (register control) ........................................... 74 rcon (reset control) ...................................... 53, 56 rcsta (receive status and control) ..................... 150 sspcon1 (ssp control 1) ..................................... 118 sspcon2 (ssp control 2) ..................................... 120 sspstat (ssp status) .......................................... 116 status .................................................................... 52 stkptr (stack pointer) ............................................ 38 summary ................................................................... 46 t0con (timer0 control) ........................................... 93 t1con (timer1 control) ........................................... 97 t2con (timer2 control) ......................................... 101 t3con (timer3 control) ......................................... 103 trise ........................................................................ 88 txsta (transmit status and control) ..................... 149 reset ............................................................... 25, 179, 217 timing diagram ....................................................... 248 retfie ............................................................................ 218 retlw ............................................................................ 218 return .......................................................................... 219 revision history ............................................................... 287 rlcf ............................................................................... 219 rlncf ............................................................................. 220 rrcf ............................................................................... 220 rrncf ...................................... ...................................... 221
pic18cxx2 ds39026d-page 296 ? 1999-2013 microchip technology inc. s sci. see usart. sck .................................................................................. 121 sdi ................................................................................... 121 sdo ................................................................................. 121 serial clock, sck ............................................................. 121 serial communication interface. see usart serial data in, sdi ........................................................... 121 serial data out, sdo ....................................................... 121 serial peripheral interface. see spi setf ................................................................................ 221 slave select synchronization ........................................... 125 slave select, ss .............................................................. 121 sleep .............................................................. 179, 185, 222 software simulator (mplab sim) .................................... 230 special event trigger. see compare special features of the cpu ............................................ 179 configuration registers ................................... 180?182 special function registers ................................................ 42 map ............................................................................ 45 spi master mode ............................................................ 124 serial clock .............................................................. 121 serial data in ........................................................... 121 serial data out ........................................................ 121 slave select ............................................................. 121 spi clock ................................................................. 124 spi mode ................................................................. 121 spi master/slave connection .......................................... 123 spi module master/slave connection ......................................... 123 slave mode .............................................................. 125 slave select synchronization .................................. 125 slave synch timing ................................................. 125 slave timing with cke = 0 ...................................... 126 slave timing with cke = 1 ...................................... 126 ss .................................................................................... 121 ssp .................................................................................. 115 block diagram (spi mode) ...................................... 121 i 2 c mode. see i 2 c. spi mode ................................................................. 121 associated registers ....................................... 127 block diagram .................................................. 121 spi mode. see spi. sspbuf ................................................................... 124 sspcon1 ................................................................ 118 sspcon2 register ................................................. 120 sspsr ..................................................................... 124 sspstat ................................................................. 116 tmr2 output for clock shift ............................ 101, 102 ssp module spi master mode ..................................................... 124 spi master./slave connection ................................. 123 spi slave mode ....................................................... 125 sspcon1 register .......................................................... 118 sspov ............................................................................. 139 sspstat register .......................................................... 116 r/w bit ..................................................................... 129 status register ............................................................... 52 stkptr register ............................................................... 38 subfwb .......................................................................... 222 sublw ............................................................................ 223 subwf ............................................................................ 223 subwfb .......................................................................... 224 swapf ............................................................................ 224 synchronous serial port. see ssp. t tablat register ............................................................... 57 table pointer operations (table) ...................................... 57 table read operation, diagram ........................................ 55 table write operation, diagram ........................................ 55 tblptr register ............................................................... 57 tblrd ............................................................................. 225 tblwt ............................................................................. 226 timer0 ................................................................................ 93 clock source edge select (t0se bit) ....................... 95 clock source select (t0cs bit) ................................. 95 overflow interrupt ...................................................... 95 prescaler. see prescaler, timer0 t0con register ........................................................ 93 timing diagram ....................................................... 249 timer1 ................................................................................ 97 block diagram ........................................................... 98 block diagram (16-bit r/w mode) ............................. 98 oscillator .............................................. 97, 99, 103, 105 overflow interrupt ................................ 97, 99, 103, 105 prescaler. .................................................................. 98 special event trigger (ccp) ..................... 99, 105, 110 t1con register ........................................................ 97 timing diagram ....................................................... 249 tmr1h register ................................................ 97, 103 tmr1l register ................................................. 97, 103 timer2 .............................................................................. 101 associated registers ............................................... 102 block diagram ......................................................... 102 postscaler. see postscaler, timer2. pr2 register ................................................... 101, 112 prescaler. see prescaler, timer2. ssp clock shift ............................................... 101, 102 t2con register ...................................................... 101 tmr2 register ......................................................... 101 tmr2 to pr2 match interrupt .................. 101, 102, 112 timer3 .............................................................................. 103 associated registers ............................................... 105 block diagram ......................................................... 104 block diagram (16-bit r/w mode) ........................... 104 t3con register ...................................................... 103 timing diagrams acknowledge sequence timing .............................. 142 baud rate generator with clock arbitration ............ 136 brg reset due to sda collision ............................ 146 bus collision start condition timing ................................. 145 bus collision during a repeated start condition (case 1) ........................................... 147 bus collision during a repeated start condition (case2) ............................................ 147 bus collision during a start condition (scl = 0) ......................................................... 146 bus collision during a stop condition .................. 148 bus collision for transmit and acknowledge .......... 144 i 2 c bus data ............................................................ 259 i 2 c master mode first start bit timing ................ 137 i 2 c master mode reception timing ......................... 141 i 2 c master mode transmission timing ................... 140 master mode transmit clock arbitration ................. 143 repeat start condition ........................................ 138 slave synchronization ............................................. 125 spi mode timing (master mode) spi mode master mode timing diagram ......................... 124 spi mode timing (slave mode with cke = 0) ......... 126 spi mode timing (slave mode with cke = 1) ......... 126
? 1999-2013 microchip technology inc. ds39026d-page 297 pic18cxx2 stop condition receive or transmit ...................... 143 time-out sequence on power-up ........................ 32, 33 usart asynchronous master transmission ........... 156 usart asynchronous reception ............................ 158 usart synchronous reception .............................. 161 usart synchronous transmission ........................ 160 wake-up from sleep via interrupt .......................... 186 timing diagrams and specifications ................................ 246 a/d conversion ........................................................ 262 brown-out reset (bor) ........................................... 248 capture/compare/pwm (ccp) ................................ 250 clkout and i/o ...................................................... 247 external clock .......................................................... 246 i 2 c bus data ............................................................ 257 i 2 c bus start/stop bits ...................................... 256 oscillator start-up timer (ost) ............................... 248 parallel slave port (psp) ......................................... 251 power-up timer (pwrt) ......................................... 248 reset ..................................................................... 248 timer0 and timer1 ................................................... 249 usart synchronous receive (master/slave) ................................................. 260 usart synchronoustransmission (master/slave) ................................................. 260 watchdog timer (wdt) ........................................... 248 trise register .................................................................. 87 pspmode bit ...................................................... 85, 90 tstfsz ........................................................................... 227 two-word instructions example cases .......................................................... 41 txsta register brgh bit ................................................................. 151 u universal synchronous asynchronous receiver transmitter. see usart. usart ............................................................................. 149 asynchronous mode ................................................ 155 associated registers, receive ........................ 158 associated registers, transmit ....................... 156 master transmission ....................................... 156 receive block diagram ................................... 157 receiver ........................................................... 157 reception ......................................................... 158 transmit block diagram .................................. 155 transmitter ....................................................... 155 baud rate generator (brg) ................................... 151 associated registers ....................................... 151 baud rate error, calculating ........................... 151 baud rate formula ......................................... 151 baud rates, asynchronous mode (brgh = 0) .............................................. 153 baud rates, asynchronous mode (brgh = 1) .............................................. 154 baud rates, synchronous mode ..................... 152 high baud rate select (brgh bit) ................. 151 sampling ......................................................... 151 rcsta register ...................................................... 150 serial port enable (spen bit) ................................. 149 synchronous master mode ...................................... 159 associated registers, reception ..................... 161 associated registers, transmit ....................... 159 reception ........................................................ 161 timing diagram, synchronous receive .......... 260 timing diagram, synchronous transmission ........................................... 260 transmission ................................................... 160 associated registers ............................... 159 synchronous slave mode ........................................ 162 associated registers, receive ........................ 163 associated registers, transmit ....................... 162 reception ........................................................ 163 transmission ................................................... 162 txsta register ....................................................... 149 w wake-up from sleep .............................................. 179, 185 timing diagram ....................................................... 186 using interrupts ....................................................... 185 watchdog timer (wdt) ........................................... 179, 183 associated registers ............................................... 184 block diagram ......................................................... 184 postscaler ................................................................ 184 programming considerations .................................. 183 rc oscillator ........................................................... 183 time-out period ....................................................... 183 timing diagram ....................................................... 248 waveform for general call address sequence ............... 133 wcol .............................................................. 137, 139, 142 wcol status flag ........................................................... 137 wdt ................................................................................ 183 www, on-line support .................... .................................. 5 x xorlw ........................................................................... 227 xorwf ........................................................................... 228
pic18cxx2 ds39026d-page 298 ? 1999-2013 microchip technology inc. notes:
? 1999-2013 microchip technology inc. ds39026d-page 299 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
ds39026d-page 300 ? 1999-2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39026d 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 1999-2013 microchip technology inc. ds39026d-page 301 pic18cxx2 pic18cxx2 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support part no. ? x /xx xxx pattern package temperature range device device pic18cxx2 (1) , pic18cxx2t (2) ; v dd range 4.2v to 5.5v pic18lcxx2 (1) , pic18lcxx2t (2) ; v dd range 2.5v to 5.5v temperature range i= -40 ? c to +85 ? c (industrial) e= -40 ? c to +125 ? c (extended) package jw = windowed cerdip (3) pt = tqfp (thin quad flatpack) so = soic sp = skinny plastic dip p=pdip l=plcc pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18lc452 - i/p 301 = industrial temp., pdip package, 4 mhz, extended v dd limits, qtp pattern #301. b) pic18lc242 - i/so = industrial temp., soic package, extended v dd limits. c) pic18c442 - e/p = extended temp., pdip package, 40mhz, normal v dd limits. note 1: c = standard voltage range lc = wide voltage range 2: t = in tape and reel - soic, plcc, and tqfp packages only. 3: jw devices are uv erasable and can be programmed to any device configu- ration. jw devices meet the electrical requirement of each oscillator type (including lc devices). data sheets products supported by a preliminary data sheet may have an e rrata sheet describing minor operational differences and recom- mended workarounds. to determine if an erra ta sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip worldwide site (www.microchip.com)
pic18cxx2 ds39026d-page 302 ? 1999-2013 microchip technology inc.
? 1999-2013 microchip technology inc. ds39026d-page 303 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 1999-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620769676 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
ds39026d-page 304 ? 1999-2013 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 11/29/12

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